CMOS High Resolution Wideband Phase-locked Loop Circuit Design

With the development of integrated circuit,and the application environment of IC is complicated.Phase-locked loops are an important part of many electronic systems,so the application environment of phase-locked loops are also strict,especially in extremely low temperature.On the one hand,the reliability of the chip is reduced in extremely low temperature.On the other hand,the process library does not support extremely low temperature range in chip design.Therefore,the designs and applications in extremely low temperature are not found,and designs in extremely low temperature are urgently needed.Although technology library does not support the extremely low temperature,the circuit working condition can be to predict by means of temperature extending in extremely low temperature.In addition,in the circuit and layout design adjustable circuits are used to adjust the work condition of the circuit under low temperature.Due to wide frequency range of the clock signal output of wideband phase-locked loop which is crucial module circuit in applications such as high-speed broadband data transmission interface and so on,to provide accurate and high quality clock signal.Ring oscillator used in PLL can achieve broadband output,but the higher gain of ring oscillator will deteriorate the noise performance of PLLs.In this paper,a current control oscillator is used to reduce the gain of the oscillator by several controlled current band to achieve the goal of wideband output.The working frequency of divider is one of the fastest modules in phase-locked loop.It is hard to realize high speed and wide frequency division in wideband phase-locked loop.The traditional divider structure is limited by the asynchronous reset logic,which makes the working frequency slowly.In addition,wide range of frequency division lead to complicated circuit structure.In this paper,a frequency divider based on shift register is proposed,which can work at high frequency and achieve wide frequency division.This paper describes a wideband phase-locked loop(PLL)circuit design,which is used for high-speed asynchronous data interface wide working temperature by adopting temperature epitaxy and optional circuit with 0.18?m CMOS process.This circuit has the characteristic of wide frequency output range and high frequency resolution.The circuit input 3~24MHz clock signal,Step is 3MHz,and output 54 MHz ~ 1GHz clock signal with 50±5 percent duty-cycle,periodic jitter is less than 20 ps.After the circuit pre-simulation,the layout is implemented and post-simulation verification is completed.The PCB design and chip testing are performed.PLL chip test results meet the requirements,the periodic jitter of only 7.31 ps at-26 ?,providing certainly reference for extremely low temperature circuit design.