Research On Resistive Memory Model And Layout Design

Memories play an important role in the modern semiconductor industry. Only DRAM (dynamic random access memory) and Flash possess 15 percent of the total marketing. The need for the non-volatile memories is being enlarged along with the promotion of the portal equipments. With conventional memories approaching their scaling limit, the next-generation memory has attracted extensive research effort. Recently, significant research and development efforts have focused on two-terminal resistive devices, including chalcogenide phase-change materials (1), doped-SrZrO3 (2), ferroelectric PbZrTiO3 (3), ferromagnetic Prl-xCaxMnO3 (4), binary metal oxides (5), and even organic materials (6).Among the novel resistive memories, phase change memory and binary metal oxides memory are promising for their advantages, such as good compatibility with CMOS process, simple cell structure, and good scalability etc. The main issue of PRAM is the relatively large programming current, resulting in larger-scaled size of the driving transistors as well as larger peripheral circuit, which is unhopeful. Therefore, the characters of RRAM make it more excellent in the future.In this paper, we investigate into the layout design of RRAM (Resistive Random Access Memory) and a compact HSPICE macromodel for RRAM (Resistive Random Access Memory) in the quest for high density solutions of next generation nonvolatile memories. On evaluating the possiblity of layout optimization of resistive memory cell, we propose and realize the maximum size for the cell under different read/write voltage. We propose solutions of the deocoder aimed at addressing the pitch of array. In order to validate the application of resistive material in a memory array and its peripherals, we implement an HSPICE model based on dual-channel model for the resistive memory cell.