High Speed ​​low Power Fifo Memory Circuit Design And Layout To Achieve

An unavoidable problem of modern IC (Integrated Circuit) design lies on multi-asynchronous clock existing in communication design between the systems and the outer circle chips. Adopting the asynchronous First in First out memory to satisfy the demand of the high-speed data transmission between systems is a kind of simple and effective solution. The First in First out (FIFO) memory has been widely used in many fields such as high-speed data acquisition, multi-processor interface, and high-speed buffer memory of communications and so on. Currently, SRAM memory research in our country is not advanced, FIFO as a special SRAM, the reports concerning its productions are less except that there are some reports on small capacity asynchronous FIFO memory, to say nothing of the reports regarding larger capacity and high-speed low-power FIFO memory chip. In this paper, the design and realization methods of the high-speed and low-power of the FIFO memory was discussed in detail, at the same time, the original chip RAM array module was redesigned to realize high-speed and low-power of the FIFO memory and to adapt the new technology requirements. Therefore, this paper mainly focused on the RAM array modules design, including memory cell and sense amplifier.The classification of semiconductor memory and development of SRAM were firstly introduced in this paper. The necessity of designing lower-power and design techniques were also summarized followed by analysis the basic structure of FIFO memory and briefly introducing the FIFO memory modules and circuits. The low-power design of FIFO memory was then discussed in view of system structure. During the process of designing SRAM cell, this paper has also deeply studied characters of the SRAM resistance load memory cell (6T-2R) and pMOS load memory cell (8T) of dual-port FIFO memory, and carried out an optimal design for 8T memory cell size in consideration of the operating speed and stability. The 8T memory cell layout was designed for CSMC 0.5μm double poly triple metal technology, at the same time, the array design method for reducing memory power and improving memory speed was discussed in this paper. A new sense amplifier with high-speed and low-power was successfully designed based on the results of comparing three kinds of sense amplifiers during the process of designing sense amplifier.At last, this paper carried out a simulation to the whole circuit of 4k×9bit FIFO memory after simulating each sub-circuit of chip. The result showed that, if the chip can be optimized by the SRAM cell and Sense amplifier, it can work stably at the 50 MHz clock frequency, its chip power and speed were improved remarkably. Its design principle can be used to design other FIFO memory with larger capacity, and may be useful for research and development of future FIFO memory.