| In recent years, RFID-related products are widely used in the field of automatic identification. Low frequency and high frequency RFID technology is quite mature. But its recognition distance is very short, usually only a few centimeters. It’s suitable for close-contact automatic identification system. Ultra high frequency(UHF) RFID system’s recognition distance can be several meters. It greatly enriches its application scenarios, such as being applied into the field of logistics to achieve goods tracking and management. As the key element of RFID system, reader chip contains radio frequency circuit, analog baseband circuit and digital baseband circuit, etc. There are a few mature products in market nowadays. It is monopolized by a few foreign companies. China doesn’t have good performance products now. Many companies and universities begin to join the research of UHF RFID reader chip.Based on the ISO 18000-6C protocol, this article completed the design of digital baseband circuit of receiving link for reader chip. The major work is as follows:1. Compare the commercial UHF RFID reader chips and some universities’ research. Complete the specification of digital baseband circuit of receiving link and the structure of it according to the protocol.2. Analyze the modules in the structure in theory. Simulation is processed in MATLAB to verify some key modules.3. Use hardware description language VHDL to implement all modules. Behavioral simulation is done in Modelsim.4. Verify the designed circuit on FPGA platform. Digital baseband circuit is connected to the RF circuit to communicate with tags wirelessly.5. Under the TSMC 0.18μm process, the circuit described in VHDL has been synthesized. Static timing analysis is done according to the timing requirements. Simulation and verification are done using netlist. Layout design is made in Encounter. Parasitic parameter is extracted to do static timing analysis and post-simulation.The reader chip’s digital baseband receiving link that based on this structure can receive tag’s returned signal whose BLF is between 40 kHz and 640 kHz. It just adds a small amount of resource consumption compared with the single rate design. To solve the problem of speed deviation of tag’s signal, it adopted a digital phase-locked loop(DPLL) structure to implement symbol synchronization. It can save a lot of hardware resource compared with the correlator array structure. |
