Design And Implementation Of FPGA-Based Rf Transceiver Experiment System

With the development of communication technology, more and more college pay attention to teching relevant to wireless communicaton technology.For Wireless communication experiment courses, good experiental platform is essential. Therefore, building a comprehensive experiental platform for wireless communication is meaningful to improve students’ understanding of wireless communication technologies,boost innovating ability and project quality.The experimental platform is a superheterodyne radio transceiver experimental platform, drawing software radio design. Transceiver parameters andworking mode can be controlled by software, with software-programmable features. The hardware structure takes into account the superheterodyne architecture and zero IF architecture to meet the versatility and compatibility.The challenge of hardware platform are mixed-signal circuits and signal integrity.By optimizing the layout, this design isolated digital chips and analog chips to increase the isolation, optimized power modules, reduced the power supply ripple, thereby inhibiting the spread of noise and improved the SNR ratio of the system. Baseband module choosed ALTERA’s cyclone III chip toprocess baseband signal, combined with a ARM chip as the control chip. Digital to analog conversion and analog to digital conversion using dedicated high-speed communication Tx DAC and Rx ADC chips, modulation and demodulation of the baseband signal selected ADI orthogonal frequency converter, the receiver baseband section using a agc chip to control the gain, the local oscillator source using PLL methods. The system itself can communicate in 140 MHz, with RF front-end, 2.4GHz-2.48 GHz communicationcan be achieved.The experimental platform cancarry out duplex communication.Transmitter and a receiver’s baseband signal program are running on a FPGA chip.We choose Verilog as hardware program language to implement these algorithms. System design using top-down design approach, the whole system is divided into several modules, the next module is divided into several sub-modules, in this way,we designed a clear structured system.The transmitter’s baseband signal processing includes video signal acquisition, parallel-serial conversion, amplitude modulation, pseudo-random coding, pulse shaping filtering algorithm; the receiver’sbaseband signal processing includes a carrier synchronization, symbol synchronization, a pseudo-random decoding, amplitude demodulation, and the string conversion, LCD drivers and other algorithms. The cores algorithmsof baseband signal processing are FIR filters, carrier synchronization, bit synchronization. Efficient use of IP core implements the FIR filter, greatly improving design efficiency. Carrier synchronization and bit synchronization methods are used for feedback control of synchronization more accurate.