FPGA Design And Implementation Of Two-channel Transceiver Based On SDR

Along With the 4G technology being put into commercial use recently,people's demand towards multimedia business growing rapidly,modern mobile communication has entered a new era.At the present stage,it is urgent to improve the efficiency of wireless communication system significantly,with the guarantee of communication quality to be the premise.Based on this,with the combination of software radio technology with large-scale field programmable logic device FPGA,the design and implementation of the channnelized transceiver are fulfilled.Undoubtedly,the digital channelized transceiver is an important part of Software radio architecture and it becomes more and more attractive in the communication field for it can greatly improve the effectiveness of communication.The multi-channel transceiver can process simultaneous signals in real time by separating signals in frequency domain.The main purpose of the design is try to improve the reliability of communication system without increasing complexity of system realization and hardware resource.And realize the function of channelized transceiver through software and hardware simulation.In this paper,the explanations of mobile radio channel environment are firstly made.Based on the classical Jake model of the wireless fading channel,we introduces randomness to the three parameters,so,we can obtain a new model,which statistical characteristics is really close to the values of theoretical calculation,what's more,the paper also gives the BER characteristics of the 64 QAM modulation signal in rayleigh fading channel.Then,the paper introduces the foundational theories in software radio,such as bandpass sampling theory,multi rate digital signal processing theory etc.It also studies software radio's core technology----the digital down/up converter's principle,in the meantime,we constructed DDC/DUC simulink models and made spectrum analysis for the signal during the course of DDC/DUC.At last,the essay comprehensively explained the concept of channelized digital transceiver as well as its classical mathematical model.Besides,the classical mathematical model of the multi-channel transceiver has been implemented in the MATLAB software platform,through the time-domain waveform comparison between the input and the output signals,the validity of model is verified.Through realizing the multi-channel transceiver,I found the interference between different channels,makes BER performances communicationsystem become worse.I made a few improvements to the filter in theoretical model for the channel division in order to reduce the interference between different channels,which dramatically improved the system reliability with out increasing complexity of system realization and hardware resource.On this basis,in the ISE10.1 software environment,the project design and implement the functional modules of the DDC/DUC technology and the transceiver model by using Verilog HDL language.In the meantime,the design using the Modelsim simulation software simulates all the modules and the whole transceiver system.Finally,waveforms and spectra belonging to communication system's significant modules,as well as some simulation results characterizing system's reliability performance,are obtained from simulink and Modelsim software.Analysis shows that the simulation results accord with design expectations;therefore,the realization of two-channel transceiver based on SDR in the FPGA universal hardware platform has been fulfilled.