Font Size: a A A

PCI High-speed Data Acquisition Module Design

Posted on:2015-07-11Degree:MasterType:Thesis
Country:ChinaCandidate:X H FengFull Text:PDF
GTID:2308330473453377Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
High speed data acquisition as an important part of electronic information technology has been used in many fields. Such as communication, test equipment, remote sensing, information security and other field.Meanwhile PCI bus as a common used Peripheral Component Interconnect bus, provides a convenient for high-speed data acquisition module in test and measurement instruments system integration.The topic of this paper is PCI Express data acquisition module design. The paper focuses on how to achieve high-speed data acquisition system design. The contents in this paper are shown as follows:Firstly, proposed the scheme of parallel sampling technology to design high-speed data acquisition, by studing how to improve the sampling frequency of data acquisition system. And in this design, I used two single-channel 500 MSPS ADC chips to achieve 1GSPS data acquisition circuit. And then analyzed the influence of the sampling clock for high-speed data acquisition performance, and designed a high-precision, lower jitter sampling clock circuit for dual channel parallel combination sampling system. After analysised the requirement of high-speed data acquisition system, I designed a high signal to noise ratio and perfect dynamic range analog circuit.Secondly, in this design implemented data storage circuit, which is based on DDR2 SDRAM SO-DIMM, according to the requirements of system storage depth and speed. And achieved read and write DDR2 memory control logic though FPGA. At same time, I achieved the design of PCI interface circuits by using the dedicated PCI interface chip PCI 9054. And designed control logic between local bus and PCI interface bus.At last, after I researched how to improve the performance of parallel data acquisition system, i find the reason which causes channel errors. And then complete the design of error correction logic to calibrate the channel errors.The issue ultimately the input signal bandwidth of 200 MHz, 1GHz sampling rate of data acquisition. The data which is sampled can be storage, calibration and transfer though the data acquisition system. The design is meet the requirements of the design specifications and achieve the intended purpose.
Keywords/Search Tags:high-speed signal acquisition, parallel sample, channel error, FPGA, PCI
PDF Full Text Request
Related items