The Design Of High-speed Data Acquisition And Processing Module Based On CPCI Bus

With the rapid development of modern testing instruments and automatic testingtechniques, the requirement of developing highly performance, stable andintegrated-easy testing instruments has been urgent. Data acquisition&processingsystem serves as the critical part of automatic testing techniques. Its sampling rate,memory depth, resolution, flexibility and stability raised much attention. Since the bussuch as PXI/Compact PCI, Compact PCIE and VXI based data acquisition module isintegrated-easy and stable, it has been widely used in the field of automatic testing andindustrial automation. Therefore，it is significant for the entire test system that CPCIdata acquisition and processing module is studied in the view of improving thebandwidth, real-time sample rate and memory depth.From the perspective of hardware implementation and digital logic design, thispaper discussed the high speed data acquisition module of CPCI bus, which includes thelogic and circuit design of storage of data acquisition, the design of DDR2SO-DIMMcontroller, the design of CPCI interface circuit and the logic design of digital signalprocessing. To be specific:1. Proposed the scheme of constructing ADC400MSPS sampling by one chip ofdual channel ADC based on the exploiting of the alternative parallel samplingtechnology.2. Analyzed the effect of sampling clock on sampling performance. The scheme of1.5GHz high frequency clock generation and conversion program is designed andimplemented according to the system sample clock theory.3. Designed the signal acquisition front-end channel. Realized the highsignal-to-noise ratio, high dynamic range, and controllable signal gain and\orattenuation analog signal path.4. According to the requirements of system storage depth and speed, finished thetask of hardware implement based on the DDR2SDRAM SO-DIMM and logic designof DDR2controller. The controller is able to adaptively match (choose) the time andaddress bit wide via reading the SPD information from the DDR2SDRAM SO-DIMM. 5. Completed the design of CPCI interface circuits and implementation of locallogical interface by using the dedicated PCI interface chip PCI9054.6. Improved the acquisition accuracy and anti-noise performance via the logicdesign of over-sampling and digital filters.This design achieved the control of DDR2SO-DIMM’s, which is able to store andprocess the collected data and meets the requirements of design specification.