A Research On Bitstream Readback-Based Test Method For Embedded Ip Cores In Virtex Ⅱ

As repeatability programming feature of the FPGAs (Field Programmable Gate Array), they are widely used in aviation, aerospace, communications, medical and other fields. With the continuous advances in integrated circuit process technology, FPGA has increasingly high level of integration, increasingly lower low-power, increasingly powerful, therefore, with respect to ASIC (Application Specific Integrated Circuit), the disadvantage of FPGA is reduced continuously and the advantage of FPGA is revealed gradually. Not only FPGA has integrated a large number of logic gates in internal, but also has integrated a large number of IP cores, such as Block RAMs, multipliers, DLLs, etc. And the development direction of FPGA is moving towards to SoPC (System-on-a-Programmable-Chip). At the same time, in order to ensure the reliability and stability of the FPGA, FPGA tests are increasingly being taken seriously. Test methods of logic resources and embedded IP cores in FPGA are researched by many scholars of home and aboard, and many test methods are proposed.In this paper, from the reliability issue of embedded IP in FPGA, on the basis of our laboratory developed test system which is based on boundary scan and readback, we have researched the test methods of Block RAM, multiplier in Virtex II FPGAs of Xilinx. The main contents of this paper contain several parts, including the following:(1)、 Reading Xilinx official documents, we will have a research on the principle and structure of embedded IP cores Block RAM, multiplier in Virtex II FPGAs, and have a functional testing for Block RAM, multiplier better.(2)、 Our laboratory have developed a test system based on boundary scan and readback, the test system hardware structure is simple and only needs an USB-JTAG cable, the main parts of the test system are software which cuts the cost of hardware testing as maximum extent as possible.(3)、 Reading relevant documents, on the basis of our laboratory developed test system which is based on boundary scan and readback, we propose the test methods of Block RAM, multiplier respectively, and the test methods will be verified by our test system.In this paper, on the basis of our laboratory developed test system which is based on boundary scan and readback, by account for the actual structure of Virtex Ⅱ FPGAs and reference to the existing test methods, we have proposed the concrete test methods of Block RAM, multiplier respectively. And by combining our test system with the test methods, the embedded IP cores in FPGA will be test automatically.