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Boundary Scan Circuitry In The Fpga Design

Posted on:2010-02-14Degree:MasterType:Thesis
Country:ChinaCandidate:Q Y LuFull Text:PDF
GTID:2208360275482790Subject:Microelectronics and Solid State Electronics
Abstract/Summary:
FPGA is the abbreviation of the Field Programmable Gate Array. As the semi-custom circuit in the field of the Application Specific Integrated Circuits (ASIC), on one hand, FPGA solves the disadvantages of the custom IC, on the other hand, FPGA conqueres the limit of gate number brought by Programmable Logic Device (PLD). Nowadays FPGA is used in more and more fields. However, with the increasing of FPGA scale and the decreasing of its package, the tests of designs and applications become harder and harder. But, boundary-scan technology can solve these problems. It applies DFT to silicon chip. And it also supports system level, board level and chip level tests. It was defined as IEEE 1149.1 standard, which was Joint Test Action Group (JTAG).Boundary-scan circuit in this paper is indispensable in FPGA. In chip, it arranges register unit and control circuit around the internal functional circuit. And it completes the internal functional test and exterior interconnection test for devices by the logical control of some pins. It is required to meet user's needs as follows: firstly, it could check up faults in circuits; secondly, users could programe and strat up FPGA by the boundary-scan block; finally, it allows users to readback the configuration data of FPGA by boundary-scan circuit. Compared with other boundary-scan circuits, it has more functions and better performances.This paper is about the design and realization of the boundary-scan circuit in the FPGA. This subject comes from Hi-Tech Research and Development Program of China and General Equipment Headquarters. The objectives are to design the boundary-scan circuit used in FPGA and to achieve functions previously mentioned, such as circuit inspection, configuration and readback. Boundary-scan technology was studied first in theory, and then the configuration and readback of Virtex-E series FPGA were studied next in theory. We paid more attention on the boundary-scan circuit in the FPGA designed using 0.18μm 1.8V/3.3V mix-techniques. Based on the above mentioned work, the global simulation was accomplished together with JTAG. The simulation result indicates that JTAG met the requirements, and the performance of designed JTAG catchs the foreign similared products.The FPGA with boundary-scan circuit, on one hand, the chip's reliability is improved and it allows users to check up the internal functions and external connection of FPGA, on the other hand, the function of the FPGA is advanced, which make it possible for the design to meet advanced international standards. It is significant for us to develop full-featured, high-quality FPGA chip with Chinese independent intellectual property rights.
Keywords/Search Tags:FPGA, Boundary-Scan Test, Configuration, Readback
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