| With the rapid development of semiconductor technology, the complexity and the integration of FPGA has got a big improvement. But the substantial increasement in the subsequent test cost and test time highlights the growing problem for FPGA testability. So how to guarantee the reliability of FPGA is very essential among current development trend. For now, the main methods of FPGA testing are as follows: traditional hardware testing method, testing method based on ATE, testing method based on BIST and testing method based on boundary scan. Each of above methods has unique advantages, but also has its flaws. For example, the process of traditional hardware testing method is complicated and time-consuming, the ATE based test method is fast but the cost is high and BIST based test method needs to spend a lot of manpower on the design of testing circuit. Method based on boundary scan also has a limit on I/O number and testing speed. So finding a new testing method which has less cost and faster testing speed is very imminent.In order to promote the development of FPGA testing technology, optimizations in the testing objectives, tesing speed, testing reliability and stability of the platform has been done in this paper, based on the existing platform in the lab, which has a great improvement for it. Besides, in the paper we also have finished the design of testing platform based on the ARM embedded system, which expands the application field of the platform and enhances the flexibility and diversity of the platform.The main contents of this paper are as follows:(1) Based on the Xilinx technical documents and combining with the existing test platform, the bitstream readback, analysis and fault location and diagnosis for the FPGAs of XCV600, XCV1000 in Virtex series and XC2V1000, XC2V3000 in Virtexâ…¡ series is realized. And the automatation of this process is also finished.(2) Based on the deep research of partial bitstream readback, the bitstream readback of CLB and BRAM is realized and is applied in the testing platform, in order of improving the testing speed.(3) Optimizations in the architecture and process of testing platform is finished in purpose of improving the speed and reliability of the platform.(4) In base of the existing test platform, GUI graphical Interface which integrates multiple operations and owns different working modes is designed for the purpose of improving usability and efficiency of the test platform.(5) In base of the existing test platform for the PC version, designs of the embedded testing system which consisting of the hardware platform and software programs is finished. |
