Theories And Methods Of The Virtex Fpga-test Research

The paper selected Xilinx Virtex XCV100 as an instance to analyze the theory and algorithm of functional testing of FPGA base on SRAM. Point to kinds of functional modules and net architectures build the fault model, analyze the algorithm, generate the test vectors, routing and place. Then synthetically evaluates the costs and efficiency through by count the test coverage, period time, complex of algorithm and hardware resources. Main technologys include: the test algorithm for RAM on chip, test logic resources of FPGA with path scan chain or Bundary-Scan, build BIST to test funcational module or route resources, build the test pattern and count the coverage for FPGA. Point the net testing, develop some unique structure. For instance, MBIST of global long line and 4 bit bus, hex-line or single line test structure. This paper also deeply researched the algorithm to generate the test pattern for these architectures. Base on these researches, especially creative place and route architecture can effectively descrease test time and the cost of hardware resource. Even easier build the test code. For some modules, this paper illustrates the applicable range depand on the actually situation. The final target of the project is what achieve high fault coverage and efficiently test for mass produce. Some of testing theorys and methodologys in the paper also can be applicated other ones that has the similar architecture, likely Virtex, Virtex II or more advanced series.