Time-sharing Alternating Adc Clock Mismatch Digital Calibration Algorithm Research And System Implementation

As the digital signal processing technology widely used in the broadband wirelesscommunication, biomedical and modern high-speed measuring instruments etc., thedemand of high-speed, high-resolution and low power ADC is increasing. Due to thesample-and-hold theory, however, a single ADC can’t achieve high-speed and high-resolution at the same time. Using several pieces of ADC to process the analog signalalternately is an effective way to improve conversion rate, however, because of theimperfect clock distribution, signal path difference and parasitic effects, offset, gain andtime mismatch take place in a time-interleaved ADC. These mismatches significantlyreduce performance of TIADC system. The digital calibration technique has been anattractive and effective way to deal with these mismatches.This work contains four main contributions. First, a through research of time-interleaved ADC sampling theory is given and an equivalent error model is established,which is essential for studying the digital calibration algorithm and designing theTIADC hardware system.Second, several digital calibration algorithms of time mismatch are presented,include estimation and correction one. In order to obtain the channel mismatch, twomain approaches for doing so are called foreground and background techniques arepresented. Once the time mismatch has been estimated, this information is used todesign a compensator. Thus the differentiator-multiplier cascade structure is introduced.To use the DMC in an application requiring a low system delay, the reduced delay DMCstructure is presented.Third, a calibration circuit for four-channel12-bits,400MSPS TIADC is designed.The design of FFT module, IFFT module, CORDIC module and DMC module areelaborate design and optimize, which make the time mismatch got a sound correction.Simulation results show that the TIADC system with ENOB over11bits and SFDRimproved by47.46dB in the input140.1MHz sine signal.Finally, to demonstrate the digital calibration algorithm, a prototype system12-bits 400MSPS time-interleaved ADC has been design. Four12-bits105MSPS sub-ADCsAD9233are used in the system. After calibration, an average ENOB improved by3.7bits and SFDR improved by23dB.