The Design And Implementation Of High Speed Interface Among The Processing-cores Based On FPGA

With the growing demand for information transmission by the users, the required bandwidth and throughput in baseband signal processing is increased rapidly, which gives a serve challenge to the design of the data transmission interface. The traditional parallel transmission techniques can not meet all the requirements of high bandwidth, high speed and high reliability simultaneously. At this point, the high-speed serial transmission techniques arises at the historic moment. GTX interface and Gigabit Ethernet interface are two important techniques for high-speed data transmission.The hardware scale and design complexity are increased significantly for the multi-processors implementation based on networks-on-chip(NoC) infrastructure, which exposes the logic resource limitation of a single chip(FPGA or ASIC). Meanwhile, the parrellel processing mechanism can divide a complicated task into sevral sub-tasks and allocated them to different processors respectively, then the task can be solved by the cooperation amony multi-processors. These all need the high speed interface design among chips and multi-processors. This thesis took the advantage of the scalability of the NoC infrastructure, and extended it to connecting the FPGA boards via the high speed serial interface. Firstly, the technique specifications of high-speed GTX interface is introduced. Then in the step of high-speed serial interface design, the Aurora protocol and a proposed protocol are analyzed and compared. Finally, base on the design requirements, the proposed protocol is adoped, and the frame formats for the data transmission and the monitored states collection between the processors are designed,which ensure the real time and reliability demand.With the continuously Internet technology innovation and progress, the demand of the Ethernet transmission applications developed rapidly,and the applications of embedded communication system based on Ethernet is becoming more and more important. As the third generation of Ethernet technique, Gigabit Ethernet(GE) interface inherited many of the advantages of previous Ethernet technique, and also has many new features. Thus, Gigabit Ethernet interface is widely used. This thesis introduces the Gigabit Ethernet transmission technique, studies the Xilinx PCS/PMA and Tri-Mode MAC IP cores by simulation. Then the verifications of GE interfaces are carried out on a FPGA-array platform. The successful data communication between FPGAs shows the correctness of the GE interface design. Then the data transmission between the FPGA-array platform and PC via BCM5396 GE-switch chip is tested. By observating the register information of GE-switch, debugging the design code, the communication between FPGA and PC is achieved.Finally, in the FPGA-array platform with Xilinx Kirtex-7 as its key chipset, we implement the LTE baseband processing based on the NoC prototype. The functionalities of the GTX interface and the GE interface are verified, and the performances are tested.