Design And Implementation Of Hign Throughput Parallel Turbo Decoder

Turbo codes has been widely used in variety of aspects since its introduction in 1993, and it was adopted as one of the channel coding schemes in 3G systems for its excellent performance in low to moderate Eb /N 0 region. However, because of the complexity of the soft information based iterative decoding algorithm and the decoding delay, there must be some trade off between complexity, delay and performance degradation when design and implement Turbo decoders. To meet the requirements of up to 100Mbps information throughputs and low delay, there's no time to delay to improve on the Turbo decoding techniques.In this thesis, we firstly introduce Turbo codes in several aspects and discuss the parallel decoding scheme, while focusing on the contention-free interleavers. Secondly, a type of interleaver based on permutation polynomial over integer rings is studied and its related mathematical theorem and design criterion are presented. Specifically, a decision theorem is proved and some interleaver patterns with good performance and MCF property are given, which paves the way for further theoretic study and hardware implementation. Thirdly, we introduce a concatenated coding/decoding scheme using single parity check product code as its component codes, with random interleavers and a very simple iterative decoding algorithm, this coding/decoding scheme can achieve considerable BER performance. Finally, the FPGA design and implementation of Turbo decoder are detailed, with a parallel sub-block decoding and pipeline structure to achieve high throughput, and the interleavers, which is constructed on permutation polynomials over integer rings, can consume the least resources and cause the minimum interleaving delay. The Verilog...