Turbo Product Code And FPGA-Based Implementation Of Its Shortened Codes

Because of its outstanding performance, Turbo product codes (TPC) proposed in 1994 has aroused people's interest widely. TPC are efficient error correcting codes that offer a wide range of flexibility in terms of code rate, performance, and hardware complexity, and will be widely applied in communications. The following contents give the summarization of the main work.The encoding and decoding principles of TPC will be researched firstly in this paper, and then the iterative decoding algorithm based on Chase decoder is discussed. Several improved algorithms are introduced. A general matrix structure for shortened TPC and its decoding algorithm are also described.By computer simulation, we discuss the factors which have effect on the performance of the decoding of TPC. Furthermore, this dissertation compares the Chase-Pyndiah algorithm and the improved algorithms.The design and implementation of shortened TPC encoder and decoder are detailed based on FPGA. The decoder has been developed on Xilinx Virtex-4 XC4VLX60 FPGA device and VHDL with utilization 7% of the logic resource and 9% of the memory resource. The data throughput of 14.17 Mbit/s can be achieved with the maximum working frequency of 142 MHz.