Design Of Digital Down Sampling Filter For Sigma-delta ADC

The research and design of digital down sampling filter in Sigma-Delta ADC is introduced in the paper.With the increasing scale of integrated circuits and the advantages of digital signal processing such as high precision, powerful and easy to implement. Thus many originally implemented by an analog circuit functions can now be realized by digital circuits. As the connection of the analog world and the digital world, ADCs are widely used in digital communication systems. The Sigma-Delta ADC Has been widely used in the field of high-precision signal processing due to the advantages of high resolution and high cost performance.Sigma-Delta ADC is mainly constituted by two parts, the decimation filter Sigma-Delta modulator and a digital, Sigma-Delta Modulator and Digital decimation filter. By using the oversampling and noise shaping techniques, Sigma-Delta modulator can increase the SNR of modulation systems and reduce the quantization noise power within the signal band. On the other side, Digital decimation filter will convert the the digital modulation signal which has passed through Sigma-Delta modulator into a Nyquist sampling rate signal. The Sigma-Delta modulator determines the accuracy of Sigma-Delta ADC and the digital decimation filter determines the rate, area and power consumption of the entire circuit.The principles and structure of the Digital low-pass filter are studied in this paper. And the paper presents an efficient design and implementation of a digital decimation filter with a down-sampling ratio of 256, which can be used in Fourth-order Sigma-Delta modulator circuit. By comparing the FIR filter and IIR filter performance and structure of the FIR filter is selected as the design of digital decimation filter structure.The proposed digital decimation filter consists of Cascaded-Integrated-Comb(CIC) filter and three-stage cascaded Half-Band(HB) filter. Cascaded-Integrated-Comb(CIC) filter has adopted a new five-stage cascaded structure with a down-sampling ratio of 32,and each Half-Band filter that with a down-sampling ratio of 2.Through the research and comparison of various filters, we have design eda new CIC filter which can effectively reduce the need to extract the clock signal circuit module and it can be a great help to Improving circuit performance, reducing system power consumption and saving the costs on hardware.The design and implementation of digital decimation filter start from system modeling and simulation in MATLAB with all levels of filter amplitude-frequency response curves required, we can get the circuit structure of each filter. On this basis, we use Verilog HDL language on RTL-level design of the digital decimation filter and Modelsim on its functional simulation. Then add constraints using Synopsys Design Compiler, the netlist files obtained were imported into SOC Encounter to place and route. The whole design fabricated in the process of TSMC 0.18?m CMOS technology with chip area 21.2?1.2mm,SNDR 88.2d B.