The Process Integration And Optimization For LDMOS

Thanks to the growing demand for low-power, small size, and function integrated devices, power integrated circuits has been developing rapidly. With the low-power and easy combination feature with the integrated circuit technology, it is widely accepted that Lateral Double-diffusion MOSFET has a widely application and an excellent market perspective.This thesis focuses on the process of the high-voltage integrated circuit developed on the 0.18μm standard CMOS technology platform, the GOI characteristics of the LDMOS, and the isolation problem between the LDMOS and the other MOS devices.The main content includes:A:Process adjustment problems were discussed during the integration of the LDMOS with the low voltage CMOS:how to use a minimal change to obtain satisfied performances of the low voltage CMOS and LDMOS devices integrated on the same chip.B:A rapid thermal oxidation was used to resolve the Poly Hole problems of the poly-silicon gate in LDMOS. Double Liner Oxide process and double HF Dip process were conducted to eliminate the influence of the STI divot on the LDMOS gate oxide layer thickness. The anti-breakdown performance of LDMOS has been greatly improved with the solution of these two major problems.C:Discussion of the reasons for failure of isolation between LDMOS and LDMOS, as well as medium and low-voltage MOS devices and LDMOS:A local ion implantation method was used to improve the isolation among the same type LDMOS in same well; DNW structure was used to improve the isolation between the LDNMOS in different well; Inverted well process, a local ion implantation under pick-up, Guard Ring structure were adopted to improve isolation among the different type LDMOS; Add HVNW outside medium and low-voltage well to improve the isolation among LDMOS and medium and low-voltage MOS.