FPGA Architecture Library Generation And Verification

An FPGA chip named FDP3P7 has been developed by State-Key-Lab of ASIC and System at Fudan University. The target of this thesis is to generate the programmable logic devices architecture library and verify it automatically for the chip. In Cadence Virtuoso platform, we used SKILL language for the second development, and partially created automation for building architecture library. By this way, we can reduce the human’s error and improve the efficiency of research.In this thesis, the first chapter briefly introduces the fundamental architecture and principle of FGPA, digital circuit design process based on FPGA. The second chapter introduces the development of EDA technology and its role in FPGA design flow, and the characteristics of EDA tool language SKILL, including basic grammar and data structure. The third chapter introduces the programmable interconnect resources and architecture libraries which are app] ied in the design. The fourth chapter introduces how to use SKILL language program to generate the bottom cel] library and extract the high fanout nodes automatically. The fifth chapter introduces how to validate the cell library to make sure it is consistency of software modeling. The sixth chapter introduces how to extract the logical location of TILE block in core level. The last chapter is summary and prospect.