Study On Improved Fibonacci Series DAC Design Technology

With the rapid development of information technology, digital communication system has claimed an ever-growing share of the information transmission, so that a greater demand is created for the performances of digital-to-analog convertor(DAC) as one of the key components. High speed, high resolution and broadband DAC have become a hot topic of research. The current-steering DAC is widely used in high-speed and high-resolution fields because of its intrinsic high speed and driving capability. However, its characteristics are affected by various factors, which make the chip design difficult.This paper focuses on the design difficulties and studies the key techniques which are implemented and validated. A 12-bit 100MS/s segmented current-steering DAC which based on SMIC 0.13 μm CMOS process is proposed. In this circuit, 6+6 segmented structure which high 6-bit utilizes thermometer code while low 6-bit DAC uses improved Fibonacci series is established after the analysis, optimization and comparison of four encoding methods and making a compromise between glitch, area and power consumption.And it has dual channels under 1.2V/3.3V dual power supply with 20 m A full scale output current and 0.263mm2 area. In analog part, a PMOS Cascode structure which increases the output impedance of the current source mirror is employed. Differential switches ensure the current path always exists, and the pseudo transistor is connected to the output port for reducing the clock feed-through effect. In digital part, one 6-7 decoder is needed because of the low 6-bit improved Fibonacci series DAC. After optimizations of the truth table,logic expression and grouping scheme, the low 6-bit is divided into 3+3 which the minimum 3-bit denote the 7-unit respectively while the middle 3-bit control 8-1 selectors,and the output signals are synchronized, cut down glitch and to increase the ability of switch drivers by latches.Cadence Spectre is used for the DAC circuit design and simulation, and Cadence Virtuoso, Calibre and Matlab play the role of design and verification of the layout. The results of post-simulation show that INL/DNL is ±0.3595LSB/±0.3039 LSB, SFDR is up to73.92154 d B/73.15604 d B for 15.625MHz/48.4375 MHz input signal frequency, and the total power consumption is 78.54 m W which prove the superior performances of improved Fibonacci series DAC that can be widely used in wireless communication field.