Design Of 16 Bits MCU Based On Low Power Optimization Technique

Recent years, the applications of MCU become more widespread among industrial controling, with the continuous development of integrated circuit manufacturing technology, the integration and speed of the chip improve greatly but also the power consumption per unit area of the chip has been on an upward trend, therefore, power consumption has become a factor that must be considered for all IC designers, appling the low-power optimization techniques to design a lower-power MCU has been the main direction of market’s demand of industrial control chip.The main work of the paper is: Applying the low-power optimization techniques to the design of MCU. The paper mainly studied an ultra-low-power design process of SH6601. Firstly Paper described the background of low-power design optimization, overview the domestic and international technology development and current status of low-power digital integrated circuit design, and studied the power source of digital IC and different optimization methods of different power sources, and analyzed the low-power optimization methods respectively from the system level, the algorithm level, RT level, gate-level, layout-level and circuit-level, and choose the appropriate optimization methods which are applied to the design of the MCU; Secondly paper elaborates the system architecture, functional modules and low-power design ideas of MCU, including design of system architecture, division of system software and hardware, chip clock technology, design of DMA controller and operand isolation techniques,and discussed the design process and its function verification of mode controll er and clock controller of MCU; Finally paper compared the power consumption of chip before and after using different optimization methods, including clock gating, operand isolation, achieving CRC respectively with software and hardware, and described the measured power of chip in different modes. The main findings of chip design:1. The chip has a 80251 core with Harvard architecture and pipelined architecture, and integrates hardware random number generator, and hardware DES encryption and decryption circuit, with high integration, high anti-interference, high reliability and ultra-low power consumption. In order to improve running speed, support for running the program in RAM, and integrated interrupt and reset controller to allow the CPU to respond in different situations timely.2. The chip has three operating modes, including Active mode, Idle mode and Low power mode, users can select the appropriate operating mode depending on the application to get the lowest power consumption. To the clock controller, depending on the application select the highest performance requirements chip 16 MHz and 32 KHz crystal clock module to achieve a stable output of the system clock is switched with no glitches.3. Studying the effect of low-power optimization methods. Preliminarily verified affect of optimization methods in low-power MCU design by simulation, which uses the register level clock gating reduces power consumption by 17.5%, using operand isolation reduces system power consumption by 15%, and hardware CRC algorithm to achieve than software CRC algorithm saves 50 times more computing time.4. The chip uses TSMC 0.18μm technology library, has passed the flow sheet, power test results, Low power modes: a minimum of 0.6μA @ 3V, Idle Mode: 40μA / MHz @ 3V, Active mode: 260μA / MHz @ 3V, meet design specifications, the experimental results verify the feasibility and effectiveness of the design method.