A Study Of Direct Digital Frequency Synthesizer With High SFDR Based On Multi-channel Interpolation Of Xidian University

In the modern electronic system such as communication and radar,the role of signal generator is more and more important.The design of high performance signal source has become the bottleneck restricting the development of modern communication,radar and high precision measurement system.Direct digital frequency synthesis(DDS)is a hotspot in the field of frequency synthesis.It has many advantages such as high precision and highfrequency resolution,easy hardware implementation and fast frequency switching.At the same time,DDS system has its shortcomings,its bandwidth and spurious become the most important aspects of its development.Therefore,countless scholars and engineers on the frequency synthesis technology research focused on DDS and DDS spurious suppression technology,these technologies are mainly based on the DDS structure and the algorithm improvements.The frequency synthesis technology and the DDS principle and structure is illustrated in this thesis,the DDS design and physical realization of high SFDR based on multi-channel interpolation are completed.In this thesis,the DDS core adopts the modified CORDIC algorithm and the ROM lookup table to realize the phase/amplitude conversion,at the same time,the effective phase bit width of the phase accumulator truncated output is improved,the pseudo-random sequence generator Dither is added,the structure of interpolation to improve the SFDR of the DDS.For a single channel,the phase accumulator has a bit width of 32 bits and is truncated to a 19-bit input phase/amplitude converter for phase/amplitude conversion,in which the upper 3-bit octal phase compress the ROM lookup table size and the number of CORDIC rotation iterations,the followed by7-bit as the address to find the ROM table to get 1/8 round period of the sine/cosine rough value,the last 9-bit divide into three groups for excess-four CORDIC rotation to get 1/8round period of the sine/cosine fine values,afterwards,based on sine/cosine function symmetry,mirror flip to get the entire cycle of 16-bit sine and cosine value output.The DDS chip supports four kinds of work:single frequency output,linear scan output,SRAM modulation output and amplitude modulation output,so it can achieve a variety of modulation signal output.Finally,the physical synthesis and implementation of the proposed DDS core is based on SMIC 0.18?m 1P6M technology library,the timing report after synthesis has pointed out the critical timing path of the single DDS core required 3.37ns,the frequency can reach the design of 250MHz,and the maximum frequency of the 16-channel interpolation DDS can reach 4GHz.The total number of cells is 41183,the number of combinational logic cells is24760,the number of sequential cells is 15171,the number of buffer/invert is 1252,the size of the proposed DDS chip after APR physical realization is 1100×2000?m~2;the clock tree insertion delay is about 2ns,and the number of the clock tree level is 7,the maximum clock skew is 132ps.The power analysis shows that the total power consumption is658.4mW,which internal power consumption is 459.69mW,switching power consumption is 198.64mW,and the static power consumption caused by leakage current is only about0.12mW.The pre-simulation and post-simulation show that the SFDR of the DDS can reach about 103dBc at the frequency of the test,and the design requirements of high SFDR,the behavior simulation,the physical verification and the timing verification after the layout verify the logical accuracy of the designed DDS chip,the rationality of physical realization and the timing closure of the design.