Research Of Broadband Dither Technology In Pipeline ADC

Analog to digital converter(ADC)is an important module connecting the analog world and digital system,and is an indispensable unit in communication system.The pipeline analog-digital converter is widely used in wireless communications,because of its high conversion accuracy,high conversion speed and low power consumption.With the development of semiconductor process and computer technology,the accuracy and conversion speed of the pipeline ADC are increasingly demanding.Due to the existence of many non-ideal factors in the circuit design,the simple converter structure cannot meet the current requirements,so the digital correction algorithm to improve the performance of the ADC becomes the focus of the current pipeline ADC research.Dither technology as a digital correction algorithm,is an important technique to improve the performance of pipelined ADC Spurious Free Dynamic Range(SFDR).In this paper,the application of broadband dither technology to improve the pipeline ADC SFDR to improve the performance by the three main improvements:(1)to reduce the harmonics generated by ADC ideal quantization error;(2)to reduce the harmonics generated by coherent sampling;(3)to reduce the harmonics generated by the circuit mismatch.The paper firstly introduces the research significance of broadband dither technology to improve the spurious free dynamic range of pipeline ADC and the development history and research status of dither technology.Then it introduces the basic theory of ADC,the parameter index to measure ADC performance and the current common ADC Type,and the advantages and disadvantages between them;Then introduced the basic principles of the pipeline analog-digital converter,digital redundancy correction principle and non-ideal factors on the performance of the analog-to-digital converter;finally,broadband dither signal is injected in a 100 MS / s,12-bit pipeline analog-digital converter to improve its small signal linearity and other dynamic performance.A 12-bit,100 MS / s pipeline ADC is built on the cadence platform as a target ADC in the TSMC 90 nm CMOS process,a pseudo-random code is generated by a linear congruential PN sequence,converted to an analog signal by a switched capacitor array,the input path of 2.5-bit first stage is added to the input signal and introduced into the pipelined ADC.The output signal from the ADC is subtracted from the properly delayed PN-sequence signal by the subtraction circuit to produce the final codeword output.The simulation results show that the introduction of dither makes the ADC's SFDR performance significantly increase when the input signal amplitude is-30 ?-50 d BFS?...