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Cordic Algorithm-based High-performance Fft Design And Implementation

Posted on:2010-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:J Y WenFull Text:PDF
GTID:2208360302957601Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
A CORDIC based high-speed configurable FFT processor is designed and implemented in this paper. It is used in real-time data process system of Synthetic Aperture Radar (SAR) in satellites. The amount of both data and calculation in SAR system is very huge, and quasi-real-time even full real-time image processing speed is needed. So the system requires a high-speed, real-time and long-point FFT processor. The FFT in this paper is able to process 8 kinds of complex FFT ranging from 64 to 8K points, the real and imaginary parts of data are both 16 bits. The Coordinate Rotational Digital Computer (CORDIC) algorithm is adopted to realize complex multiplication. It divides the complicated multiplication into a series of simple addition and shift operations so as to reduce the system complexity and increase the working frequency. There are four Radix-4 butterfly units in the partly parallel pipeline structure, so the speed of FFT is improved effectively. In order to process real-time signal data, Ping pong SRAM and double frequency are adopted. Block floating point is used to increase the data dynamic range and solve the problem of overflow, which costs same as fixed point but achieving better precision.In the design of CORDIC multiplier, a new convenient twiddle factor generator is proposed. It doesn't need any extra ROM resources so as to save large amount of hardware. In order to read and write 16 decimated data at the same time, the SRAM is divided into smaller blocks and a conflict free address generating method is proposed, so the system speed is highly improved.This paper presents the analysis and expatiation for the FFT processor about its algorithm, structure, high-speed design method and RTL design. The FPGA verification, ASIC design and post-layout simulation are also presented to ensure the circuit function and timing. The highest working frequency achieves 125MHz. At 100MHz clock, the calculation time of 1024-point FFT is 4.41μs, the calculation time of 8192-point FFT is 37.61μs, totally fulfilling the requirement of FFT design.
Keywords/Search Tags:FFT, CORDIC multiplier, Parallel structure, Block floating point
PDF Full Text Request
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