The Research And Analysis Of Anti-fuse FPGA

FPGA(Field Programmable Gate Array)is composed of a lot of programmable logic units, some complicated and programmableto interconnect resources, the programmable I/O circuit.It can carry out various functions according to the customer’s independent programming.Base on the development of FPGA design technique and semiconductor technique, anti- fuse FPFA is coming to wide attention and application of electronic industry. Owing to its advantages of non easily city lost, low power consumption, high level of integration, stable performance, resistance to total dose and so on. It is especially suitable for military and aerospace utilizations with the high reliability and high confidentiality.This work analyzes the domestic and foreign development of the anti-fuse FPGA, and then discusses basic structure and working mode of the anti-fuse FPGA. This study also discusses the working principle of the different types of anti-fuse, including ONO and MTM types. Their programming process, programming voltage,Ohms feature, layout are analyzed in detail respectively. Herein the structure and the fusing process of ONO typeare deeplyanalyzed. In addition, the programming method and process of the fuse array are discussed. This dissertation illustrates the overall structure of the FPGA and the circuit composition, including the CLB( Configurable Logic Block), I/O module, wiring resources, clock network and JTAG. In order to understand the work of the fuse well, and present the working principle of FPGA intuitively. We make a simulation of the anti-fuse FPGA programming in respect to vertical section of the fuse. The simulation on inner modules are as follows: the functionsimulation andtime-lapse simulation of the CLB,including C_Moudle, D_Moudle and S_Moudle;the simulation of charge pump including the oscillator frequency conversion circuit,the auxiliarible circuit of access to electricity and the voltage regulator circuit.Through the simulation of last three circuits, we obtain a charge pumpwith high efficiency andlow power consumption; The I/O simulation are carried on TT, FF and SS conditionswith-55, 27 and 125℃, meeting the criterion of Actel SX-A Family FPGA’Data book. Meanwile we make a verification of the anti-fuse control function in I/O, including the slope controlling, pull-up pull-down resistor controlling and voltage clamping circuits; JTAG simulation is for the working method of the JTAG, which emphatically discusses TAP meaned the state machine, the core of JTAG. Finally, we complete the layout design of the whole circuit module. The layout is from TSMC(Taiwan IC manufacturing company, TSMC) 0.18 um process, the VCCA voltage of 1.8 V, VCCI I/O voltage is 3.3 V. Our work analysis for after the anti-fuse of the FPGA provides reference.