Design And Implementation Of Digital IF Receiver Based On FPGA

With the development of Software Radio Technology and Radar Technology, the Digital IF Processing Technology has made steady improvement. Function of Digital IF Processing Technology is also becoming increasingly powerful. The role of Digital IF Processing Technology has become more and more important in the area of Automotive Electronics and Radar Electronics. As we all know, the Digital IF processing Technology are moving forward while FPGA features are also developing fast. FPGA can provide a very stable and flexible hardware platform for electronic technology. Based on the point above, the research direction is introduced. It is the design and realization of digital IF receiver.It is important to do the theoretical study of Digital Signal Processing to achieve the appropriate theoretical knowledge of the algorithms of Digital Filter and the principles of AD. We also have to know how to use digital algorithm to achieve NCO used in this thesis. The function of AD is converting analog signals to digital signals. The style of AD sampling of this thesis is Nyquist sampling. Center frequency of input analog signal is 30MHz and the signal bandwidth is 2MHz. Time of the linear frequency modulation will be 50us and AD sampling frequency is 80MHz. There are a lot of ways to design and implement Digital Filter. We can use Window and Function Frequency Sampling Method or Chebyshev Approximation Method to achieve the desired digital filter in this thesis. FIR Filter used in this thesis will be based on Chebyshev Approximation Method. FIR filter is utilized to achieve four times Decimation and 8 times Decimation of signal to extract the data rate of the signal to 2.5MHz. Structure FIR filter implements is polyphase filter structure. CORDIC algorithm is used to design and realize NCO. CORDIC algorithm is a real-time algorithm and does not require a lot of memory unit. Frequency of NCO is 30MHz. This thesis will also use scientific simulation to study the feasibility of the design in this thesis. The main simulation tool includes Matlab, Quartus and Modelsim. Matlab is a powerful simulation software. It can be utilized to analysis Digital Filtering Algorithm and obtain the appropriate digital filtering coefficient of Digital Filter. The entire system will be analyzed by Matlab simulation to demonstrate the correctness of the entire program. Quartus is also a important simulation software to FPGA design, which can describe the logical behavior of FPGA by program language and send the program into the corresponding FPGA chip. Modelsim is similar to Quartus. While Quartus just can simulate the timing of FPGA, so we have to use Modelsim to simulate the function of FPGA and can quickly find out the design is correct or not.Through theory and scientific simulation, the design which meets the requirements can be obtained. Design needs to be implemented on the hardware platform. The final Digital IF Receiver hardware is realized based on the design of PCB board diagram and hardware diagram. Through the test and analysis of hardware and practical engineering applications, Digital IF receiver can meet the design requirements. It can be effectively applied to the radar field of Digital IF Receiver. The design of this thesis can be a reasonable reference and offer useful information to other RF and IF applications.