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Research Of Software Radio Digital Receivers Based On FPGA

Posted on:2010-09-15Degree:MasterType:Thesis
Country:ChinaCandidate:H W LiuFull Text:PDF
GTID:2178360275451653Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In modern electronic systems, digitization has become the inevitable trend of development.The digitization of the receiver is an important part of digital electronic system,so it is significant on its research.With the rapid development of the micro-electronics technology and digitization theory, high-speed digital-IF receiver has become possible.This paper research a FPGA-based software radio platform ,which focused on the design and achievement of digital-IF processing units. FPGA devices is designed with the flexibility and short development cycles and low development costs, so it is widely used in various communications systems. Compared to the traditional structure of DSP Serial, FPGA design can be pipelined, parallel processing of data, so FPGA have great advantages on real-time processing and the large data amount.In this paper, first analyzes the current development trends and status of software radio technology and for the problem of DSP speed,bring up a a FPGA-based software radio platform . This paper is focused on the FPGA realization.With in-depth analysis of software radio based on the theory, focused on and completed the realization of two modules of the receiver of FPGA-based software radio: digital down-conversion-related modules and digital modem modules. Among them,the numerical control oscillator(NCO)of the digital down-conversion module adopts the direct numerical control oscillator frequency synthesis (DDS) technology.The high-performance decimation filter is composed of integrator comb Filter(CIC), half-band filter (HB),and FIR filter.Greatly saving resources and increasing the run rate by improving the internal register bits using Hogenaur "cut off" theory.The FIR filter and HB filter are designed by (DA) distributed algorithm,its speed only relates to the data width, and only binary addition and subtraction and division operations, both to reduce the system resources and significant savings of computing time to achieve efficient real-time processing.In the end of the article, the entire system Matlab simulation verifies the correctness of system design concepts.During the process of key modules design of the system,firstly program using "verilog" language based on the design of specific indicators,and then it is compiled in the Quartus software, running timing simulation testing, and compared the results of Matlab simulation to verify the correctness of the design.
Keywords/Search Tags:Digital Down Converter, FPGA, efficient decimation filter, DA distributed algorithm, Hogenaur "cut off " theory
PDF Full Text Request
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