Programmable Digital Down Conversion In Software Radio Receiver Research And Design,

The foundamental idea of Software Radio(SWR) is to establish a opne, standard and modular universal hardware platform where the A/D converter is moved as closed as possible to antenna and all of the communication function is realized by software. The aim is to research and develop a high flexible and adaptable communication system. The technology of making A/D converter has been advanced fast. The A/D working bandwidth has covered the intermediate frequency (IF) supporting high sampling frequency and wide dynamic range and long length. The wireless receiver technology has been developing from digital baseband to digital IF. Thus it is possible to implement the wide bandwidth digital IF receiver based on bandpass sampling theory.In this paper, a programmable digital down converter (PDDC) applied on wide bandwidth digital IF receiver is design and implemented by FPGA. This PDDC can translate digital IF signal to baseband, extract desired channel, decimate the sample sequence, multirate converter and channel shape. Using Top-Down design method, the whole PDDC function is divided to many units implemented respectively and organized to the module library. When applying PDDC on receiver, these function modules are selected, configured and optimized to a complex module a designed to satisfy the wireless system demand. This PDDC based module library and re-configurable structure are more flexible and programmable than classic ASIC down converter.PDDC in this paper adopts digital quadrature down converter based on polyphase filter and uses programmable sampling clock synthesizer based on phase lock loop embedded in the Cyclone FPGA to select channel and implement digital down converter. This structure doesn't multiply the received digital signal with numeric control oscillator by multiplier, which improves the data throughput capacity. A programmable decimation and interpolation ratio module onnected with multistage cascade integrator comb (CIC) filter is designed to implement high efficient decimator and interpolator. A modified CIC compensation filter is realized to reduce the CIC's passband error that distorts the original signal. Four half band filter (HBF) decimation modules are designed which can cascade connected to implement 2K decimator. The distributed algorithm(DA), CSD code and modified reduced adder graph(RAG) algorithm are used to realize constant coefficients filter such as time aligned filter, HBF and raised cosine pulse shaper constant. The channel shape filter is implemented by a programmable TDD inverse FIR filter, which makes good use of FPGA resource and display the FPGA parallel ability. All of these module upper mentioned are function simulated and sequence analysis by FPGA develop tools. At last, the PDDC designed in this paper is applied on GSM/EDGE/WCDMA multimode digital IF receiver whose system is simulated by ADS2002C. The results show it can satisfy the system demand.