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Wideband High Sensitivity Digital Receiver

Posted on:2003-07-12Degree:DoctorType:Dissertation
Country:ChinaCandidate:R ZhangFull Text:PDF
GTID:1118360095960119Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In the detecting and intercepting of Radar signals, wideband digital receiving technology is an important trend. Wideband digital high sensitivity receiver (WDHSR) places its Analog Digital Converter (ADC) as near the antenna as possible to cover a wide survey band. With data rate converter, the high data rate after ADC is decreased while the information bandwidth of the target bandpass signals is kept well. By applying programmable device, like Digital Signal Processor (DSP) etc, more signal processing methods can be carried on to get detail information about target signals. Such kind of hardware platform makes the signal processing be able to be implemented by changing different software on the programmable device. The concept of this receiver is like a software radio. But there lie many differences. In Radar signal interception and receiving, no pre-information of the target signals is provided within a complicated magnetic environment. According to the characteristics of Radar signals, this dissertation focuses on resolving the rate gap between ADC and DSP. A few approaches are proposed in this paper.The essence of data rate conversion is multi-rate signal processing technology. But in wide band digital Radar signal detection and receiving, the high data rate after ADC requires alteration. Two approaches are studied in this paper: frequency-guided receiver and channelized receiver. The frequency-guided receiver requires target signal's carrier frequency, gained by frequency measurement, to induct data rate conversion. By splitting the frequency spectrum within ADC overlay, channelized receiver made up of filter banks bandpass filtering, down converting and decimating correspondent part without pre-known parameter of target signals.This dissertation studies two kinds of frequency-guided receivers by applying the following two approaches: bandpass sampling (BS), wideband efficient digital downconversion (WBEDDC). Uniform BS and non-uniform BS are studied. It is proposed that because thebandpass ample rate shifts with the carrier frequency and bandwidth of the target signal, DSPs with varying processing clock speed are required. This brings great trouble in hardware implementation. Based on WBEDDC, two approaches are proposed: blind frequencies covering and signal receiving with low frequency estimation precision. With these two methods, signals are received by doubling filter's passband bandwidth without hardware structure change and bandpass sampling the signals after filtering. With fixed output data rate, high processing efficiency, the hardware implementation is much easier using low speed device.Multi-stage filtering and decimation are proposed to be applied in channelized receiver. A no-blind frequency area channelized receiver is proposed. By comparing amplitude detection and energy detection, the output detection methods and the suitable application occasion of each are discussed. Multi-stage filtering and decimation are used to decrease the filter order caused by signal's normalized narrow bandwidth. The no-blind frequency area channelized receiver has following virtues: no blind frequency area, simple structure without multi-stage realization, low filter order and easy to be realized.In bandpass sampling of multiple signals, multi-stage decimation is proposed to be used. By overlapping the filter transition band of each stage, the filter's order is greatly reduced. In multiple signals receiving based on WBEDDC, two multiple signals receiving approaches and their applications are proposed: the frequency shifting arithmetic and the double bandwidth method. Improvement is proposed to reduce multipliers used in WBEDDC. The hardware designs of data rate conversion system based on the three approaches, bandpass sampling, WBEDDC, digital channelized receiver are studied. The idea of combining high speed ADC, high speed memory array and polyphase structure of data rate converter is proposed. The compare of available high speed programmable devices is made in hardware implementation...
Keywords/Search Tags:wideband digital receiver, bandpass sampling, digital down conversion, polyphase structure, filterbank, multi-stage decimation, FPGA, blind frequency area receiving
PDF Full Text Request
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