Scan Chains Optimization Design Of 3D Chips Under The Influence Of Mid-Bond Test

With the continuously improving of the technology level,the integrated device unit number on a single chip increases dramatically,and the feature size continuous increasing.The growth of interconnection lines between units not only slows the working speed down,but also enlarges the chip area.Both of them have a strong impact on the further improvement of integrated level and speed for integrated circuits.Then,three dimensional integration technology arises at the historic moment.Three dimensional integrated circuits realize vertical interconnections by means of through-silicon via,which can effectively decrease the chips area,improve the packaging density,greatly improve working speed of the chips,bring down the power consumption and delay of the chips.However,with the increase of complication level of chips,a series of problems such as fabricating cost,test problems,fault coverage and reliability problems caused by heat become increasingly prominent.How to effectively minimize test time and cost of 3D chips,which will be the top priority of hot research topic in the numerous problems.This thesis is aimed at reducing test time by scan chains optimization design of 3D chips.The main contributions and innovation points are briefly summarized as follows.1.Research on parallel testing techniques in a single mid-bond test under the influence of fault coverage.To minimize test time and cost in mid-bond test for three dimensional embedded cores,this thesis takes the die-to-die stacked design as an example and treats the three dimensional semi-finished chip as a measured object in mid-bond test.Then according to the different requirements of various cores? fault coverage,we restrict the number of overall test input/output ports and do research on the influence that fault coverage acts on multiple scan chains balanced design.On this basis,this thesis proposes a parallel test interval optimization algorithm for mid-bond test based on greedy strategy,which synthetically consideres fault coverage and scan chains lengths.The proposed algorithm can reduce test time and test cost during a single mid-bond test.Experimental results for the ITC?02 SoC test benchmarks show that test time in this thesis can be reduced by 29.76% when compared to the existing solutions which simply consider balancing the scan chains lengths.2.Put forward scan chains co-optimization design of 3D chips based on cores hierarchical placement.Using improved simulated annealing algorithm based on cores hierarchical placement realizes cores hierarchical design of 3D chips,which can make cores density in each layer as evenly as possible.On the basis of it,using scan chains allocation algorithm in which mid-bond test reutilizes scan chains in pre-bond test co-optimize overall test time and reduce hardware overhead.Experimental results for the ITC?02 SoC test benchmarks show that test time and hardware overhead in this thesis can be respectively reduced by 27.26% and 89.70% under the constraints of TSV.Besides,the placement of cores in each layer is more homogeneous.