The Research Of Adaptive Test Algorithm And Its Implementation Based On Boundary Scan

As the emergence of very large scale integrated circuit,high density chip packaging technology and the multilayer PCB,the physical accessibility to IC pins and internal chip logic is gradually weakened or even disappears,conventional probe has been unable to use.On the other hand,the electronic market is more and more strict with product reliability and quality,the testing cost in circuits and systems is rising ceaselessly in the proportion of total spending.The conventional test methods are facing increasingly serious difficulties,the emergence of boundary scan test technology solves this difficult problem.Based on the research trend of current circuit test development,meanwhile,taking account of the actual production demand of the company,this paper studies the boundary scan test technology,especially the test matrix generation algorithm in depth.In this paper,the basic theory of boundary scanning technology is first studied,and the types of boundary scan test are analyzed,the research focuses on interconnection test.With the related concepts of interconnection test in mathematical analysis,and mathematical model is set up for the circuit faults.For the sake of convenience to analyze the test matrix generation by test algorithm,the paper optimizes the fault model,with the mathematical deduction analysis,the new fault model analysis of boundary scan algorithm has a better effect on complexity,the number of fault and so on.Then,the test matrix generation algorithm for the interconnection test is studied,and the detection performance of the existing single-step algorithm is too poor,which fails to complete the higher test requirements at the most time.Analyzing the performance indexes of each step algorithm,combining the analysis ideas of the existing adaptive algorithms,from the primary test,the test result analysis and the secondary test to optimize the W algorithm.Besides,the paper rarely takes the “line and” and “line or” logic short circuit fault into consideration at the meantime,with the test matrix compactness and completeness analysis of optimized adaptive algorithm,its detection ability is higher than the existing adaptive algorithm.Finally,the paper gets about to the boundary scan test design.First of all,combining with engineering practice,the paper mainly considers about the devices which don't have the structure of the boundary scan and completes their design for testability.In board-level interconnect design,after introducing the DFT,circuit board test coverage increases about30%,providing the hardware basis for better implementation of the boundary scanning test algorithm.Secondly,FPGA is used to build the module of the boundary scan test system,the process of the optimized adaptive algorithm is analyzed,and the test simulation of boundary scan logic is realized.The simulation results show that the algorithm is effective.