Video Acquisition And Implementation Of The Key Technology Of H.264 Coding Based On FPGA In Marine Monitoring Terminal

With the continuous development of video codec technology and integrated circuit technology, the video codec standard industrialization, especially the hardware implementation technology, will be gradually maturing, and become a new economic growth point. Hardware design and implementation of the key technology based on H.264/AVC, H.265/HEVC and AVS have very important theoretical and practical significance.Firstly, this paper has studied and analyzed the H.264/AVC encoder and video acquisition technology, focusing on the detailed theoretical analysis of three key modules of the integer transform, quantization and intra prediction. Secondly, it has designed a hardware pipeline structure of the transform, quantization and residual reconstruction module and the intra prediction module. Finally, has designed hardware circuit in Verilog HDL language, completed function simulation in Model Sim 10.2 simulation software, completed the implementation for each module on the FPGA chip of Xilinx Kintex-7 series using Vivado synthesis, and given the simulation results and the resource consumption situation of the corresponding module.The project has also further studied the H.265/HEVC integer transform and the calculation module of intra prediction, and completed the structure design and FPGA implementation of each module. Different with the general N*N size of DCT/IDCT of the H.265/HEVC that processes N pixels in one cycle, 4*4, 8*8, 16*16 and 32*32 block size of DCT/IDCT of the design can process 16, 8, 8 and 8 pixels respectively in one cycle, and has simplified the algorithm of DCT/IDCT, using no multiplier design, which can reduce the resources. The results of the synthesis implementation have showed that: the timing of integer DCT and IDCT module of the H.265/HEVC can meet the requirements of parallel processing 40 pixels in one cycle under the frequency of 250 MHz, and the processing capacity can reach 10Gpixel/s, in which, DCT module consumed 18638 LUT and IDCT module consumed 31656 LUT, occupying 19.79% of LUT resources of xc7k410tfbg900-2 chip and meeting the needs of real-time coding of 1080 P video in 60 fps.