The Hardware Design Optimization On HEVC Integer Transform And Intra Prediction Module

In order to deal with the enormous pressure brought by high-definition video transmission and storage,the International Telecommunication Union(ITU)has released the High Efficiency Video Coding(HEVC).Based on the previous generation of coding standards,HEVC has improved many techniques,including the use of larger size transform units and prediction units,more flexible coding unit partitioning and complex prediction modes.These techniques,while improving the coding rate,it will also greatly increase the complexity of the algorithm.In the field of video coding,many applications have high requirements for real-time processing.Therefore,designing a dedicated processing circuit is critical to speed up the encoding process.This article first explains the necessity of designing the hardware structure for video coding based on the existing research results,then introduces each video coding standard,and analyzes the newly introduced technical features in the HEVC standard,focusing on the computationally complex integer calculation and complex intra prediction,research content and innovation of this article are as follows:(1)Introduce the Discrete Cosine Transform(DCT)algorithm,and study the floating-point DCT fast transform algorithm used in image and video area,combined with the characteristics of the integer transform proposed in HEVC,on the one hand by using the shift-add method avoids the use of multipliers in hardware design,which helps to reduce the complexity of the circuit,and on the other hand,the use of resource reuse in the hardware circuit is reduced by decomposing the conversion of large points into small points.In terms of the characteristics of the FPGA device,the circuit area is reduced by using embedded RAM instead of the register,and the use of multiple blocks of parallel RAM to speed up the transposition process.From the perspective of rational distribution of processing order to improve hardware utilization.Finally,4k @ 30 fps video conversion processing is achieved with less hardware usage.(2)Introduce the intra prediction algorithm in HEVC and analyze the computing features in each mode.According to the characteristics of filtering operation in DC mode and Angular mode,the circuit is designed as a three-stage pipeline from the perspective of overall processing,On the one hand,the design is more structured,which is beneficial to the design of the hardware structure.On the other hand,the pipeline method improves the data throughput.For the expansion and selection of reference pixels in the relatively complex Angular mode,this paper presents a hardware-friendly reference pixel selection structure by calculating the possible reference pixel positions,avoiding the introduction of complex logic.At the same time,the use of logical cutting for Planar mode reduces the circuit delay,and finally designs a structure with 4x4 processing capacity per cycle.Compared with other study,this paper has an advantage in predicting the high proportion blocks.