HVEC Intra Coding Fast Algorithm Research And Integer Transform Hardware Design

HEVC is currently the latest video coding standard. It is developed by Joint Collaborative Team on Video Coding (JCT-VC) which is jointly formed by VCEG and MPEG organization. The core goal of HEVC is to double the compression efficiency compared with H.264High Profile, while ensuring the same quality of video image. Compared with previous coding standards, HEVC introduces many new techniques. While the coding performance of HEVC is improved, the encoding time and complexity are significantly increased. Therefore, accelerating coding speed and decreasing coding computational complexity under the premise of ensuring coding efficiency and image quality is urgent and important for the development and application of HEVC.With the rapid development of digital video technology, HD, Ultra HD video has become more and more popular. In some video applications, such as video conference, video surveillance, etc, real-time coding is required. In order to satisfy real-time coding of high-resolution video, we need to design hardware encoder with high throughput and high processing speed. Due to that HEVC encoding algorithm is complex and hardware chip design needs to minimize power consumption and hardware resource consumption and improve processing speed, it is a huge challenge to design hardware encoder for HEVC. Transform module has a large amount of computation and high complexity. HEVC adopts integer DCT transform with different sizes. Therefore, it is of great significance for HEVC hardware encoder to design HEVC transform module which has high throughput, high processing speed and can satisfy the requirement of real-time encoding.In this paper we focus on reducing the complexity of HEVC encoding algorithm and designing HEVC integer DCT transform module. The main contents are as follows:(1) For the current problem that the encoding algorithm is complex and the coding speed is slow, this paper studies fast algorithm for HEVC intra coding. HEVC coding unit (CU) uses the recursive quadtree partition method based on rate distortion cost, which brings high computational complexity. This paper proposes a fast CU partition algorithm for HEVC intra coding based on image texture. The proposed algorithm skips some CU sizes based on image texture characteristics of the coding blck. This way reduces the number of CUs whose rate distortion cost needs to be calculated. In order to verify the coding performance of this algorithm, we test this algorithm in all I frames case and compare it with HM10.0original algorithm. Experiental results show that the proposed algorithm effectively accelerates the encoding speed and performs26.08%average time saving with negligible loss of image quality and encoding efficiency.(2) For the problem that HEVC transform module has high computational complexity and needs to satisfy the requirement of real-time encoding, this paper designs HEVC integer DCT transform module and implements it on Xilinx FPGA. The hardware design adopts3stages pipeline architecture and inputs/outputs16data in parallel, which improves the circuit clock frequency and throughput. To solve the problems of large computation of multiplication in DCT and high hardware resource consumption, this paper adopts non-multiplier structure which uses shift and add operation instead of multiplication. After verification and test, the maximum clock frequency of this design is more than245MHz and the maximum throughout is more than3920Mpixel/s. Hence, the designed circuit can satisfy the requirement of HEVC real-time coding.