An Architecture Design For An HEVC Intra-frame Encoder

This thesis is used for a new video compression standard HighEfficiency Video Coding (HEVC), and aims to design a low-complexityHEVC intra-frame encoder. Compared with the last standard H.264, thecompression rate of HEVC is2times higher. Meanwhile, the complexityof HEVC is much higher than H.264. The intra prediction still plays animportant role in HEVC, when implementing an intra-frame encoder, thereare three problems lead to high complexity. The first problem is thatHEVC supports more intra prediction units and modes, calculating all theprediction units and modes will cause huge complexity. Secondly, HEVCadopts Rate-Distotion (R-D) cost for the mode decision. The computationfor R-D cost is quite high. The final problem is HEVC supports large sizetransform, which will cause many hardware resourses.To reduce the number of intra prediction units and modes requiringfine processing, the author proposed a fast selection method for HEVCintra prediction units and modes. At first, the author proposed alow-complexity HAD-based cost model and an off-line training methodwhose complexity is quite appropriate. Based on the off-line trainingresults, a prediction unit selection method is proposed and only twoneighboring levels are selected from five levels to do the fine-processing.By comparing the results of proposed HAD-based cost, the candidatemode for R-D cost can be selected. The precise HAD cost calculation canbe eliminated. In order to take advantage of the large size transforms to thecoding efficiency, the author presents the32x32prediction unitcompensation strategies. The experimental results show that proposed fastprediction unit and mode selection method can achieve more than50% encoding time reduction and the corresponding BD-rate is less than2%.To reduce the complexity of R-D cost implementation, we presented alow-complexity R-D cost estimation algorithm for HEVC intra prediction.To gain an R-D cost, a reconstruction loop is required to get the distortionvalue and the entropy coding is required to get the rate value. To eliminatethe entropy coding in the R-D cost and prevent the data dependencyproblem by the reconstruction loop, we use the transformed coefficient toestimate rate and distortion part of the R-D cost, respectively. The resultsshowed that the R-D complexity can be reduced by60%while theperformance loss is less than2.5%.To reduce the hardware resources of HEVC large size transform, weproposed a low-cost architecture for HEVC transforms. Firstly, to reducethe complexity of forward transform, the author proposed a parallel-inserial-out algorithm and the fixed number of transform results aregenerated in each cycle. The proposed architecture can be reused indifferent cycles to reduce the hardware resources. The result shows that wecan save19%hardware resourses compared with the previous work. Toreduce the complexity of the inverse transform, the author proposed areordered parallel-in serial-out algorithm. In this scheme, we reordered theoutputs of the inverse transform results in order to share the inputs ofbutterfly structure. Therefore the computation for intermediate resultscould be reduced. The experimental result shows that more than33%gatescan be reduced compared with previous work.The experimental results show that our proposed schemes can achievelow-complexity. And all the proposals could be applied to a real-timeHEVC intra-frame encoder.