The Research And Implementation Of UHF RFID Tag Chip’s Analog And RF Front-end

Radio frequency identification (RFID) is a technology to achieve automatic identification of the identified object by the use of electromagnetic induction of wireless RF signals or spatial coupling of electromagnetic propagation. In recent years, with the rapid development of the Internet of Things technology, ultra-high frequency (UHF) radio frequency identification technology, due to its characteristics of non-contact, far working distance, fast communication rate and mutlti-card identification characteristic, has attracted more and more attention. So it is becoming the research hotpot, and has quite wide application field. Thus, the study of this paper will have significant importance.This paper mainly researches and realizes the analog and RF front-end of UHF RFID tag chip, making it have the characteristics of low power, high dynamic range, high dynamic range and small size. Firstly, based on the ISO/IEC 18000-6C standard, this paper has analyzed the working principle and process of the UHF RFID system, laying the theoretical foundation for the design. Then the architecture of the tag chip is proposed, at the same time, the main points of each module and difficulties in the entire chip design are analyzed. On the basis of the above work, in accordance with the design requirements, the design of analog RF front-end circuit is carefully completed, including matching circuit, voltage doubler rectifier, shunt voltage regulator circuit, DC-DC up circuit, series voltage regulator circuit, reference voltage/current source, power-on reset circuit, demodulator, modulator and clock circuit. And the complete simulation for each module circuit has been done. Finally, according to the architecture of chip, the joint simulation of the module in the Analog and RF front-end has been done, and the layout of each module circuit’s also has been completed.Sub-threshold and low voltage design technology are adopted in the entire analog RF front-end circuit, so the power consumption of the chip is greatly reduced. The design and simulation of the chip is based on SMIC 0.18μm process. The simulation result on the Cadence spectre platform show that when the entire RF analog front-end circuit works at the center frequency of 915MHz, the operating current is about 5μA;the input signal amplitude can be 300mV-5V;the stable output voltage of power supply unit is 1.0V and 1.8V; power on reset circuit reliably outputs POR signal; the forward communication rate is 40Kbps-160Kbps; the oscillation frequency of the clock circuit is stable at 1.92MHz; each module circuit can meet the design specification of the requirements; the layout area of Analog RF front-end is 0.55mm x 0.74mm.The main features and novelties of this paper are:l)In the power supply unit, this paper has design a combination structure of RF-DC and DC-DC to provide the power for EEPROM, so that it can improve the energy utilization efficiency and save the chip area.2)Design a low voltage, low power consumption and high precision reference voltage/current source, which can generate 500mV/900mV reference voltage and 100nA reference current at the minimum supply voltage of 1.1V. The benefit of this design is eliminating the use of large resistor in the feed back network of the series regulator circuit.3) Design a demodulating circuit with the characteristics of high dynamic range and low power consumption. This demodulator can demodulate the input RF signal of the amplitude from 250mV to 5V, and its own power consumption is less than 0.7μ.W.