Key Technology Research To Experimental Platform Of 8GSPS Time Interleaved Parallel Sampling System

High speed sampling system is widely used in communication field, high speed radar signal processing field, and high energy particle physics experiments. Single analog to digital conversion chip could not satisfy the demand both high sampling rate and high resolution in the same time, because of the limitations of materials. Several same performances analog to digital conversion chips can be organized by time interleaved technology, to realize resolution invariability but sampling rate multiplied. This topic will research focused on how to improve the performance of ultra-high rate time interleaved parallel sampling system.According to the indicators of project, we design the 8 GSPS and 12 bit resolution system framework. Frontend circuit, system clock network, high speed data flow storage strategy, and channel mismatching offline compensation algorithm are further studied, to analysis of the main factors that affect the whole system performance improvement. Finally, quantitative calculation methods are offered to solve these problems. This paper main research content is as follows,1) Propose a solution that single-ended signals turns out 8 differential signals. Formula derivation is carried out to clarify the relationship between signal unbalance and spurious free dynamic range. Wilkinson power divider is compared to T matching node in the performace of signal balance. Finally we conclude the schedule of frontend signal conditioning circuit of 8GSPS system.2) Aimed at the jitter-free sampling clock of ultrahigh speed time interleaved parallel sampling system, we design a set of perfect clock network. On the condition of low jitter sampling clock, reset and synchronization of sampling channels are realized with the timing sequence controlled in the scope of the device fault tolerance. Also, the sampling phase of channels could be adjusted.3) How to ensure the signal integrity and the high speed data flow errorless are intensively researched. With simulation tool and rule of thumb, the signal reflection caused by the change in the instantaneous impedance can be worked out in an elegant way. We also use the ChipSync function of Field-Programmable Gate Array, serial-to-parallel, and large storage arrays to expand the real-time memory depth of sampling points.4) Sampling channel mismatch compensation algorithm is carried out with signal interpolation and Farrow filter. We design the experiment and simulation to verificate the algorithm. At the end of the article, the hardware of the system is implemented.