Multi-Constellation Gnss Receiver Hardware Design And Implementation

Multi-constellation satellite navigation receiver research is booming at home and abroad with the rise of the GNSS. In this paper, a receiver of that kind has been designed. The main work of this paper focuses on the receiver board’s circuit design and debugging. The receiver can handle civil signals of Beidou2, GPS and GLONASS as well as the military signal of Beidou2. It can not only receive satellite signals from different systems to provide positioning service simultaneously, but also uses the signals in an overlapped way. The receiver has high positioning accuracy, high sensitivity and rapid TTFF (Time to First Fix). The entire receiver board is about88mm in long side and57mm in wide side. It owns merits of versatility, good stability and reliability.The receiver is designed as a consolidated system. In the design procedure, the similarities and differences between the different satellites’ signals are considered deeply at first to work out a high-performance, highly integrated, cost-effective architecture. Based on this architecture, the paper introduces a RF front-end compatible with passive antenna and active antenna. A comprehensive RF channel solution for Beidou2’s military signal using a general-purpose DVB tuner and a high-speed high-resolution ADC is also described, gets this part of the design rid of dependence on dedicated RF ASIC. These three points mentioned above are the principal innovations of the paper.The main contents of the paper are as follows:1) An introduction of the development of GNSS, the research status of multi-constellation receiver and the significance of this paper;2) A brief description of basic satellite navigation theory and the characteristics of satellite navigation signals;3) The requirement analysis of the receiver’s hardware system and a demonstrated overall scheme, a complete implementation of RF front-end, digital signal processing unit, interface, power supply systems and clock network;4) Key points of the receiver’s printed circuit board design. A study of high-density printed circuit board layout method and high-speed digital and RF mixed signal routing strategy.5) A description of issues encountered during the debugging procedure, details of signal testing and troubleshooting, verification of the receiver’s overall performance and a general method of hardware system debugging.6) A summary of the whole design followed with a prospect of the receiver’s future development.