Research And Design Of If Circuit Used In Bluetooth Low Energy Rf Receiver

With the continuous development of IoT and IoT devices,wireless communication technology is one of the key technologies for the development of the Internet of Things.Due to the advantages of low energy consumption and long transmission distance,and compatibility with all mainstream operating systems,Bluetooth technology has become the main communication protocol for most Internet of Things devices,especially the application prospects of BLE widely.The intermediate frequency circuit is a key circuit module in the Bluetooth low energy radio frequency receiver.How to achieve low power consumption and high performance while meeting the requirements of radio frequency indicators has always been an important topic in the research of low energy Bluetooth chips.This thesis uses HG?0.11?m CMOS technology to design an intermediate frequency circuit applied to the low-power Bluetooth low intermediate frequency receiver chip.The intermediate frequency circuit is compatible with BLE4.2 and BLE5.0 versions,and uses complex numbers in the architecture.A cascade link of a Complex Filter and a Variable Gain Amplifier.The complex filter adopts the third-order Chebyshev I-type active filter structure,which has two intermediate frequencies and two bandwidths,and provides a gain range of10 d B.The operational amplifier uses an input stage with complementary push-pull input,which greatly reduces the circuit Power consumption.The resistors,capacitors and other devices in the filter adopt an array structure,and a Frequency Calibration Circuit is designed to tune the array so that the filter maintains stable amplitude-frequency characteristics under different process angles and different temperatures.The VGA adopts a closed-loop structure with high linearity and provides a gain range of 30 d B.A DC Offset Cancellation Circuit is designed in the loop of the VGA to eliminate the DC deviation,so as to achieve the purpose of improving the stability of the circuit.This thesis uses Cadence Virtuoso software to design the layout of the IF circuit.The layout area is 750 ?m×1200 ?m.The post-simulation result of the layout demonstrates that the IF frequency and bandwidth of the IF circuit are adjustable at 1/2 MHz and 0.5/1 MHz,and the gain range is 0? 40 d B,the gain step is 5 d B.The maximum ripple is 0.59 d B,the maximum noise figure is 36.5 d B,the minimum third-order intermodulation point is-12.5md B,and the working voltage of the entire intermediate frequency circuit is 0.59 d B at-40??85? and at each process angle of SS,TT and FF.1.5 V,power consumption is 1.77 mW.