Research Of Reconfigurable Cryptographic Algorithm Accelerator Based On Routing Table

Information security is crucial in the current rapid development of internet and information technology society, and a variety of cryptographic algorithm is the basis of encryption and decryption of the information. Facing with the poor performance and high power consumption of microprocessor and inflexibility of ASIC in encryption and decryption computation, Combined with the characteristic of cipher algorithms and reconfigurable design technology, a coarse-grain reconfigurable cryptographic algorithm processing architecture based on routing table is proposed in this paper. The main content and innovative points of this paper include:1. Analyze cryptographic algorithm process and characteristics, extract atomic operations and instantiates them as processing elements. Operating elements is taken as reconfigurable gains to reconfigure architecture with routing table and parameter table. Routing table is in charge of configuring interconnection network of operating elements while parameter table is responsible for configuring cryptographic algorithm parameters. By generating routing table and parameter table information according to different cryptographic algorithms, cryptographic accelerator is coarse-grain reconfigured to support various cryptographic algorithms.2. Map the symmetric cryptography and asymmetric cryptosystem typical algorithm RC6and RSA to the accelerator architecture. Combined with the transverse parallel and longitudinal serial flow characteristics of cryptographic algorithm processing flow, configure each configuration item content of routing table entries, reconfigure the function and structure of operating elements array to make the structure fully match the characteristics of the two cryptographic algorithm RC6and RSA.3. Take RC6, RSA and ECC as typical examples and design experiments to validate the performance, flexibility and power consumption of processing architecture. As is shown in experiments, the architecture has both the advantages of microprocessor and ASIC and it flexibly supports various cryptographic algorithms with excellent performance and low power consumption.