Equalizer. Blind Fpga Implementation

Equalizer is one of the most critical components in modern digital communication systems, which could eliminate the inter-symbol interferences while speeding up the data transmission rate greatly. With the rapid development of the radio communications, the blind equalization technique has become a hot topic in the corresponding research fields. This thesis is focusing on hardware implementation of blind equalizer, laying emphasis on a FPGA (Field Programmable Gate Array, FPGA) based implementation of fractionally-spaced equalizer adapted by constant modulus algorithm (FSE-CMA). The techniques involved for corresponding designing are discussed in detail. After that a hareware simulation system is constructed, on which the designed FSE-CMA equalizer is tested. The test results prove the feasibility of the scheme, and show that FSE-CMA algorithm is suitable for implementation with FPGA. The designed equalizer performs well in the ISI environment, therefore is valuable for communication system design.