Design And FPGA Simulation Implementation Of The Methods For Blind Signal Separation

Blind Signal Separation (BSS) technology has been developed since1990s. It involves the artificial neural networks, statistical signal processing and information theory, and other subjects of theoretical knowledge. BSS technology has been widely used in seismic reconnaissance, mobile communication, voice processing, array signal processing, biomedical engineering and other fields. BSS is aimed to estimate the original signal from the mixed signal signal when the original signal is unknown.The information maximization algorithm proposed by Bell and Sejnowski is a BSS method based on information theory.The theoretical basis of the method is Linsker’s information maximization theory. The algorithm in the performance of mixed speech signals separation is stronger than other algorithms, thus it is much more suitable for high-quality speech processing in the system of communications, multimedia and speech technology.This paper researches the BSS algorithm based on fastICA, BSS algorithm based on the biggest signal-to-noise ratio and BSS algorithm based the information maximization, and on matlab platform, simulates and achieves the two-way mixed speech signal separation algorithm based on information maximization, finally, designes FPGA implementation plan based on information maximization BSS algorithm, and completes the design of the main modules. Main tasks are as follows:(1) in-depth analysis of the infomax algorithm theory, the modular design method is divided into five modules:input module, matrix multiplication module, judge module, learning module and output module.(2) Each module is carried out on FPGA design. The design of the study module is emphasized since it is the core of infomax algorithm implementation. LUT based on ROM could implement the nonlinear function in algorithm.(3)By using the custom fixed-point number representation, the design and simulation of each module are completed, and the simulation results are analyzed.This paper uses Matlab, simulink, DSP Builder tools, and Quartus Ⅱ as the design platform, the used device is Altera Cyclone Ⅱ FPGA series, EP2C35F484C8.