In The Exchange Of New Fpga Interconnect Structure Research

FPGA has become one of the key digital system over the last two decades because of its unique programmable technology, low mask cost, shorten time-to-market and easy to upgrade. The programmable feature of FPGA is decided by its unique architecture. Among the research and development of FPGA architecture, the design of programmable interconnection is the most important, because it costs approximately70%of the chip area and60%of the signal delay.This thesis summarize the research about interconnection in FPGA, point out that the traditional fabric gain the flexibility by large redundance in space. As the scale of the chip increase, the traditional fabric soon became the bottle net of speed and density of the chip. This thesis proposed a new architecture of FPGA(Time Division Exchange-FPGA which shorten by TDE-FPGA) interconnect based on time-division multiplex, source-synchronous, pipelining, and the theory of time slot exchange. The new architecture can reduce the area of interconnection resources, play down the design complexity, improve the reliability, lay the foundation for developing high density and low power FPGA chip. It will bring enormous social and economic benefits if the research can be applied in homemade FPGA chips.Firstly, proposes the whole hardware framework of TDE-FPGA, adds time slot exchange, time division multiplex, serializer and deserializer to the traditional FPGA, and then emulated the added circuits using TSMC65nm technology library, the results show that the design of TDE-FPGA are thoroughly correct.Secondly, establish the software model of TDE-FPGA through transport the time division exchange fabric into the space interconnection fabric, based on the CAD tool VPR and modify its arithmetic and procedure, which named TDE-VPR.Finally, assess the new TDE-FPGA architecture based on TDE-VPR, place and route on TDE-VPR for20MCNC standard test circuits, compared the minimal channel width Wmin between the TDE-FPGA and the traditional FPGA. The results show that the TDE-FPGA can reduce the amount of Wmin, enhance the routability compared with the traditional FPGA, and with larger M, a better result can be obtained. And then compared the area difference based on the area model, the results show that when M=8, we can save the area of29.6%at most,15.2%in average. It proves that the new TDE-FPGA architecture can reduce the area of interconnection resources.