Design Of A2.5Gbps Serdes Receiver Front-end

The rapidly development of wire-line communications has increased the data ratealmost exponentially over the past decades. Especially in digital computing and signalprocessing field, data transfer rate has become a key bottleneck that limits theperformance of high-speed communication system.In order to meet the growingdemand for high-speed data transmission, Serdes is gradually replacing the traditionalparallel buses and becoming the mainstream of high-speed interface. Serdes is a kindof multiplexing technology that converts data from parallel to serial. As a point to pointcommunication, Serdes can achieve a much lower cost by reducing the communicationchannels and chip pins.The receiver is an important component of Serdes system. Its main function is tosample and reconstruct the received data and then achieve the conversion from serial toparallel. Jitter tolerance, signal integrity and accuracy in sampling of the receiver arecritical factors that limit the performance of Serdes. As a result, it’s significant toachieve a high performance receiver.In this paper the relevant background of Serdes is introduced at first, includingdevelopment overview, architecture and performance indicators. Then the operationalprinciple of receiver is presented. Data receiving process includes clock data recovery,channel compensation, data sampling and data reconstruction. To ensure the stabilityof the system theoretically, critical path method is applied in this design to analyzetiming delay. At last, the schematic and layout of this receiver front-end is designedusing SMIC180nm CMOS process. Simulation shows that the data rate is2.5Gbps andthe power consumption is171mW under a1.8V supply.