The Design Of8b/10b Codec And Differential Receiver Based On Rapid IO V2.0Agreement

With the rapid development of embedded technology, signal transmission rate is becoming higher and higher. However, the transmission capacity of traditional bus has not been improved as much. The development of embedded technology has been limited by high speed signal transmission technology seriously. The Serial Rapid IO is presented to solve the problem which is mentioned above. As a high speed serial communication interface, Serial Rapid IO is designed to meet the interconnection requirements of high performance embedded system. It is mainly used to build high speed DSP systems, mobile communication base stations and so on.Based on the data transmission bottleneck faced by high performance embedded system, and the advantages of Serial Rapid IO in data transmission, a lot of analysis and research work about Serial Rapid IO were done as follows:1. The structure of Serial Rapid IO v2.0protocol was introduced briefly. It could be divided into three layers, and then the details of each layer were analyzed separately.2. The details of8b/10b codec standard were analyzed deeply. The analysis included the effect of8b/10b encoding, naming and classification of encoding, detail process of encoding, calculation of encoding polarity and encoding error indication. Then8b/10b codec was designed based on the analysis results mentioned above. Specific design work included writing RTL verilog codes, simulating RTL verilog codes by Modelsim, synthesizing RTL codes by Synopsys DC with TSMC130nm CMOS process. The result showed the power consumption and area of encoder were785.9uW and0.16mm2, the power consumption and area of decoder were727.6uW and0.21mm2.3. The agreement about differential receiver was researched carefully. Based on top-down design method, firstly, the design indexes of differential receiver were extracted; secondly, the system overall scheme was proposed and then validated by simulink toolbox of Matlab; thirdly, all sub circuits were designed and simulated in Cadence with SMIC40nm CMOS process. The innovation of this design was improving equalization ability of traditional CTLE equalizer greatly by using parallel feedback low-pass network. Lastly, the layout of differential receiver was designed, and post layout simulation was done. The core area of layout was50.5um*42.8um, and the post layout simulation results showed that the average power consumption of differential receiver was2.1mW, working bandwidth was0-4GHz, the ability of equalization of receiver at2.5GHz and3.125GHz, were11.75dB and13.8dB respectively, the jitter of output signal was5.8ps. All of these met or exceeded the design targets.