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The Design Of Standard Cells In40nm

Posted on:2015-07-27Degree:MasterType:Thesis
Country:ChinaCandidate:K L ZhengFull Text:PDF
GTID:2298330452464623Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
In the nanometer process node, the critical dimension has becomesmaller and smaller, which can bring the design huge challenge. And thelayout dependence effect born with the advanced technology will largelyaffect the performance of each device. The main stream of the design isfocus on avoiding layout dependence effect. however, taking advantage ofthese phenomenon has become more practical meaning than before.The target of this research is using the layout dependence effect onthe design of each standard cell and increase the PPA (power, performance,area) parameter. Through the research on the characterization of eachstandard cell, the standard library can be divided by core cells and aid cells.According to the different feature of different cells, I change the structureof each cell and the placement on layout area to meet the largest layoutdependence profit. Almost all the modified design of the standard cells isbased on the layout level. The traditional method of the layout or the celllevel design on advanced technology can make each cell much moreaffected by the layout effect than before. In this research, discarding someold method and using the new idea according to the new technology is thecore opinion of the research. In this passage, it mainly uses multi-ODmethod to gain the better current density because of the NWE effect. Atthe same time, adding the always-off cell to some part which can make thewhole OD continuous is another method to largely benefit from the LODeffect. After all, the purely new placement of some MOSFETs to rearrangethe MOSFET is the additional solution to the WPE effect.All of the design is based on the TSMC40nm technology. After theoptimization of each basic cell, the standard cells can increase13%inspeedup. And some typical cells can have20%speedup in the FF corner.And all these methods only increase1%of the whole area. And most of theP&R placement is almost the same than before. In the same time, all these design can be keep in the1%dynamic power and the5%static power.Finally, the combined PPA parameter becomes7%better than before.
Keywords/Search Tags:Standard cell library, Layout effect, circuit design
PDF Full Text Request
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