Research And Implementation Of Synchronous Parameters Estimation Algorithm Based On Multi-carrier Mode Of DTMB System

The transmitter of GB20600-2006Framing Structure, Channel Codingand Modulation for Digital Television Terrestrial Broadcasting System wasannounced in2006, which is abbreviated to DTMB. The standard usesTDS-OFDM modulation technique, which uses a psedudo-random(PN)code headerinstead of the traditional cyclic prefix guard interval to improve the transmission rateand spectrum efficiency, and the PN frame header is used to time-domainsynchronization, the OFDM technology against frequency selective fading, however,the orthogonality between subcarriers is strict on synchronization. In this paper, thestudy on the synchronous parameters estimation algorithm based on multi-carriermode of DTMB system, and finally the designed and the realization of itssynchronous system have been implemented.First of all, several international and domestic existing DTTB standards arebriefly introduced. This paper not only emphasis on the structure of the transmitterand the receiver, the characteristics of framing structure based on DTMB standard,but also analyzes the synchronous problems and proposes the synchronousmechanism and the synchronous parameters estimation algorithm based on themulti-carrier mode of DTMB system. The algorithm uses the PN frame header toestimate the synchronous parameters in the time domain based on the timing recovery,including the frame header mode estimation, the frame header location estimation, theframe number estimation and the carrier frequency offset estimation. The algorithmprocess as follows: estimates the frame header mode based the slidingantocorrelation of the receiving sequence through three correlators first, and thendigital derivates the results in the correlator, which is related to the correspondingframe header mode, to get the coarse frame header location estimated value; estimatesthe coarse frequency offset by frequency scan algorithm with adjustable steps byusing the PN sequence A from the local PN generator, which matches the zero phaseof the frame header mode; after the reveiving data have been compensated with thecoarse frequency offset estimated value, the frame number is estimated based thecorrelation between the PN sequence A and them; then after the local PN generator generated the PN sequence B, which matches the frame header mode and the framenumber, the receving data correlate them again to get the fine frame header locationestimated value; finally, the fine frequency offset estimated value is catched based theanto-corrleration of receving data according to the fine frame header locationestimated value; the final carrier frequency offset estimated value is the result of thesum of the coarse frequency offset estimated value and the fine frequency offsetestimated value. And then validates the performance of the synchronous parametersestimation algorithm by using MATLAB simulation.From software to hardware, the hardware-platform is based on the Stratix IIseries FPGA chip EP2S90F1020C4in the designing system. And after realizating thesub-module of the synchronous parameters estimation module, joins and debugs themin the Quartus II environment, compares the FPGA and MATLAB simulational results.In order to closer to the actual receiver, the analog transmitter module is added toachieve the environment to validation through the artificial delay.