| Since the 1990s, the television is carrying out a new technological revolution; digital TV is gradually replacing analog TV. At present, there are four digital TV terrestrial transmission broadcasting standards in the world: America's ATSC standard, Europe's DVB-T standard, Japan's ISDB-T standard and China's DTMB standard. The DTMB standard was announced in August 2006 and integrates single and multi-carrier modulation modes. The multi-carrier mode adopts TDS-OFDM technology, which takes PN sequence as guard interval and OFDM modulation to transmit useful signal, and thus has an advantage of higher data rate, robustness to multipath and narrow-band interferences as well as higher bandwidth utilization.This dissertation proposes an optimized synchronization algorithm and circuit structure for OFDM-mode DTMB receivers with the objectives of lower cost, lower power and higher performance. This synchronization technology has already implemented in a DTMB demodulator chip. What is more, this design adopts PN sequence to realize synchronization in time domain, so the synchronization method is not only adapt to the OFDM-mode DTMB receivers, but also suitable to extend to single-carrier-mode DTMB receivers as well as other communication systems with PN sequence.The main contribution of this dissertation can be concluded as following:(1) Based on the research of OFDM communication technologies and DTMB standard, the architecture for the DTMB receivers is proposed and the influence of non-ideal frame synchronization, carrier synchronization and sampling synchronization to the whole system is quantitatively analyzed.(2) Proposed a synchronization algorithm for DTMB receivers. For frame synchronization, sliding correlation scheme is adopted. The synchronization is divided into two parts: capturing and tracking. First determine the frame index and then find the location of FFT window. For sampling synchronization, a full digital timing recovery loop with a new timing error detector which has constant detecting gain and larger working range is adopted. Besides, the loop bandwidth can be adjusted automatically to improve performance. For carrier synchronization, based on the analysis of the influence of very large carrier frequency offset on the correlation peak, a low-complexity and high-performance improved D-spaced carrier frequency offset estimation algorithm is presented. (3) Based on the synchronization algorithm proposed in this dissertation, the corresponding hardware structure is presented. Firstly the architecture of the three synchronization loops interleaved together is depicted, then the key modules are described respectively, which includes the correlator, SRRC filter, interpolator, down-mixer, Cordic circuit and frequency offset detector, etc. Since the correlator and SRRC filter are the two biggest area and power consumer, their circuit structures are optimized.(4) Proposed a RAM based hybrid FIR structure for the correlator. The usage of RAM, which has higher integration degree than ordinary registers, can reduce the chip area. Compared with the conventional Direct-Form or Direct-Form-Transpose FIR structure, the new structure has much lower power because only 1 / 32 of the storage units are in the flip each clock cycle. In addition, a slip window is also designed so the correlator can stop working outside the window which can realize power reduction.(5) For high-order SRRC filter, a first-add-then-shift scheme is adopted which will reduce the hardware expenses caused by intermediate computing results. Besides, the IQ interleaved structure can reuse combinational logic circuit and further reduce chip area.(6) Apply the synchronization technology in a DTMB demodulator chip. The architecture of the whole DTMB demodulator chip and its design flow is given, and the area and power consumption in both FPGA and ASIC implementation for synchronization circuit are analyzed. Finally, the chip verification platforms and the corresponding test results are presented. |
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