Full Model Gb Digital Tv Demodulator Chip Research And Design

Digital television technology is bringing up a new industry revolution worldwide. It will ultimately change the style of broadcasting programs, and meanwhile exercise a profound influence upon the development of information industry. America, Europe, Japan and Korea has offered DTV service one after the other, and China will start delivering DTV programs at the eight host cities during the 2008 Beijing Olympics. Therefore, the baseband demodulation chip, which is regarded as the kernel component of DTV system, has become intensive focus of many research institutes.This work is targeting at the demodulation chip design of China DTTB standard, which supports two transmission modes: single carrier modulation (SCM) technique and multi-carrier modulation (MCM) technique. And a novel demodulation algorithm capable of processing both SCM and MCM signals is presented. Meanwhile an optimized dual-mode demodulator architecture with low-complexity VLSI implementation cost is developed.Firstly, based on comparisons of mainstream broadband wireless communication receiver architecture and system level analysis, a dual-mode receiver architecture compatible with both SCM and MCM modes is proposed in this dissertation. The proposed architecture can realize efficient hardware sharing under two working modes, and shares the same signal processing flow.Secondly, several new demodulation algorithms and corresponding hardware structure are proposed to improve the whole demodulator performance upon in-depth investigation of synchronization, channel estimation and equalization algorithm of DTMB system. (1) The existing frame synchronization algorithm could not work properly when a large carrier frequency offset exists. A new coarse frequency estimation method is presented utilizing the shift-and-add property of PN sequence to recover the delta-like auto-correlation function of PN sequence. The coarse carrier frequency offset can be retrieved from the phase of the reconstructed correlation peak. (2) A dynamic tracking algorithm is presented to achieve robust frame synchronization path under dynamic multipath fading channel. Simulation results show that to reduce miss alarm and false detection probability. Also a new sampling offset estimation algorithm with larger estimation range is developed. The improved algorithm combines the correlation peak shift and existing method to provide actual sampling offset estimation. (3) A novel FHT-based cyclic correlator is proposed instead of the traditional matched-filter based cyclic correlator under short-echo multipath channel. The proposed architecture can greatly save area cost and power consumption due to the reduction of needed operations compared with matched filter architecture. (4) The existing channel estimation method needs several iterations and several large-point FFT units to for long-echo multipath channel. In this dissertation a novel hardware architecture which only iterates once is adopted and cyclic convolution is constructed between frame body and channel impulse response to effectively reduce hardware complexity.Finally, a complete dual mode DTMB demodulator architecture is developed on the basis of aforementioned algorithms and hardware structure. Detailed analysis of the VLSI architecture, datapath and signal processing flow, as well as module reuse information is illustrated. Then a general FPGA verification platform for DTV system is introduced and the FPGA receiver compliant with DTMB standard is tested on the above platform. The test results show that the proposed algorithms and VLSI circuit structure achieve the design requirements and has promising application value.