The Dtmb 3780-point Fft On Multi-core Dsp Platform

Since the 1990s, the television technology is carrying out a new technological innovation, simulation modulated TV is gradually replaced by digital modulated TV. In the revolution, four digital TV terrestrial transmission broadcasting standards have been brought out, for example, ATSC from America, DVB-T from Europe, ISDB-T from Japan, and DTMB form China. And all these standards have employed the OFDM multi-carrier modulation technology, which enable the system to transmit signals at a high speed and robust the Anti-multipath interference ability along with high spectrum efficiency. In the OFDM system, the FFT which modulates the signals to transmit is a key module that is critical to the performance, and its algorithm and implementaion decide the products' cost, power, and performance.Nowadays, as the Time-To-Market is more and more important to consumer electronics, the tranditional asic implementation is way to far to meet the market demands. And while the general purose processor and DSP are developping to a paralleling architecture with a higher performance, it is quite possible to implement some applications which used to be asics'fields exclusively to platforms of DSPs.With the platform of DSPs, aimed to compute the 3780FFT efficiently is the target of the thesis. The thesis has investigated in to the implementaion of 3780FFT of DTMB standard in the multi-processor DSP platform, analysed the different algorithms of FFT, compared performance of different implementaion, and fully utilized the paralleling computing capability of mulit-processor platform.The main works in this dissertation can be concluded as following:1. Investigatd into the different algorithms of FFT, such as Cooley-Turkey algoritim, Good-Thomas algorithm and Winograd algorithm. Studied the decomposition of large point, the order of small point and the combination of different algorithm.2. As the platform is non-commercial and is designed by laboratory, fully utilization of the platform features and programming speciality is studied.3. Based on the master of hardware platform features, along with study of FFT algorithm, a plan of two cluster was implemented at the hardware platform. And after simulation, a new mapping plan was implemented which utilized three clusters to boost up the parallelism and processor-to-processor communication was realized with shared memory.4. Thoroughly scrutiny and simulation of the two mapping plans have been done and research into the data and performance bottleneck was put forward, along with possible boosting strategy solution.